EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 428

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–42
Arria II Device Handbook Volume 2: Transceivers
8B/10B Decoder
Figure 1–40
Figure 1–40. 8B/10B Decoder
The 8B/10B decoder is compliant to Clause 36 in the IEEE802.3 specification,
decoding the 10-bit data input into an 8-bit data and a 1-bit control identifier. This
module is required in GIGE, PCIe, Serial RapidIO, and XAUI functional modes, but is
optional in Basic functional mode.
Figure 1–41
identifier by the 8B/10B decoder.
Figure 1–41. 8B/10B Decoder Operation
The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or
control code group on the rx_ctrldetect port. If the received 10-bit code group is one
of the 12 control code groups (/Kx.y/) specified in the IEEE802.3 specification, the
rx_ctrldetect signal is driven high. If the received 10-bit code group is a data code
group (/Dx.y/), the rx_ctrldetect signal is driven low.
shows the block diagram of the 8B/10B decoder.
shows a 10-bit code group decoded into an 8-bit data and a 1-bit control
datain[9:0] or datain[19:0]
from the Word Aligner or
Rate-Match FIFO
Recovered Clock or
Received Last
tx_clkout[0]
MSB
ctrl
9 8
j
h
H
7 6 5 4 3 2 1 0
8B1/0B Conversion
g
7 6 5 4 3 2 1 0
G
f
F
i
8B/10B Decoder
E
e
D
d
rx_dataout[7:0] or rx_dataout[15:0]
C
Chapter 1: Transceiver Architecture in Arria II Devices
RX Phase Compensation FIFO
c
Received First
to the Byte Deserializer or
B
b a
A
LSB
Parallel Data
rx_ctrldetect[0]
rx_runningdisp
rx_errdetect[0]
rx_disperr[0]
December 2010 Altera Corporation
Receiver Channel Datapath