EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 220
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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7–24
Arria II External Memory Interface Features
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DQS Phase-Shift Circuitry
f
1
Arria II devices are rich with features that allow robust high-performance external
memory interfacing. The Altera
interface features and helps set up the physical interface (PHY) best suited for your
system. This section describes each Arria II devices feature that is used in external
memory interfaces from the DQS phase-shift circuitry, dynamic OCT control block,
and DQS logic block.
If you use the Altera memory controller MegaCore
megafunction and UniPHY IP core are instantiated for you.
For more information about supported external memory IPs, refer to
Section III: External Memory Interface System Specification
Memory Handbook.
Arria II phase-shift circuitry provides phase shift to the DQS/CQ and CQn pins on
read transactions when the DQS/CQ and CQn pins are acting as input clocks or
strobes to the FPGA. DQS phase-shift circuitry consists of DLLs that are shared
between the multiple DQS pins and the phase-offset control module to further
fine-tune the DQS phase shift for different sides of the device.
®
Memory IPs allow you to use these external memory
Chapter 7: External Memory Interfaces in Arria II Devices
®
functions, the ALTMEMPHY
Arria II External Memory Interface Features
in volume 1 of the External
December 2010 Altera Corporation
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