EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 32

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–4
Figure 2–4. LAB-Wide Control Signals
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving a maximum of 10 control signals to its
ALMs at a time. Control signals include three clocks, three clock enables, two
asynchronous clears, a synchronous clear, and synchronous load control signals.
Although you generally use synchronous-load and clear signals when implementing
counters, you can also use them with other functions. Each LAB has two unique clock
sources and three clock enable signals, as shown in
can generate up to three clocks using two clock sources and three clock enable signals.
Each clock and clock enable signals are linked. For example, any ALM in a particular
LAB using the labclk1 signal also uses the labclkena1 signal. If the LAB uses both
the rising and falling edges of a clock, it also uses two LAB-wide clock signals.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock. The
LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control
signals. In addition to data, the inherent low skew of the MultiTrack interconnect
allows clock and control signal distribution.
6
6
6
labclk0
clock signals per LAB.
There are two unique
or asyncload
or labpreset
labclkena0
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
labclk1
labclkena1
labclk2
Figure
labclkena2
2–4. The LAB control block
syncload
December 2010 Altera Corporation
labclr0
Logic Array Blocks
labclr1
synclr