EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 257

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Figure 8–13. Receiver Datapath in Non-DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
December 2010 Altera Corporation
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
8–13:
1
10
For more information about the LVDS Transmitter/Receiver Package Skew
Compensation report panel, refer to the “Arria II GX LVDS Package Skew
Compensation Report Panel“section in the
Megafunction User
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
IOE
Guide.
2
PLL (4)
3
DOUT DIN
Multiplexer
Bit Slip
(Note
Clock
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
diffioclk
1), (2),
rx_inclock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
(3)
SERDES Transmitter/Receiver (ALTLVDS)
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
N
3 (DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
DPA Circuitr
Retimed
DPA Cloc
LVDS Clock Domain
P P
P P
Data
k
DIN
y
+
rx_in
8–17