EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 225

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Table 7–7. DLL Reference Clock Input for EP2AGZ300 and EP2AGZ350 Devices in the 780-Pin FineLine BGA Package
Table 7–8. DLL Reference Clock Input for EP2AGZ225, EP2AGZ300, and EP2AGZ350 Devices in the 1152-Pin FineLine
BGA Package (Part 1 of 2)
December 2010 Altera Corporation
DLL0
DLL1
DLL2
DLL3
DLL0
DLL1
DLL
DLL
CLKIN (Top/Bottom)
CLKIN (Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK12P
CLK13P
CLK14P
CLK15P
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
For Arria II GZ devices, the reference clock for each DLL may come from PLL output
clocks or any of the two dedicated clock input pins located in either side of the DLL.
Table 7–7
for the Arria II GZ devices.
through
CLKIN (Left/Right)
CLKIN (Left/Right)
Table 7–9
CLK0P
CLK1P
CLK0P
CLK1P
—
—
—
—
show the available DLL reference clock input resources
PLL (Top/Bottom)
PLL (Top/Bottom)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
PLL_B1
PLL_T1
PLL_T1
PLL_B1
PLL_B2
PLL_T2
PLL (Left/Right)
PLL (Left/Right)
PLL_L2
—
—
—
—
—
PLL (Corner)
PLL (Corner)
—
—
—
—
—
—
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