EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 244

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–4
Figure 8–2. High-Speed Differential I/Os with DPA Block Locations in Arria II GZ Devices
Notes to
(1) Not available for F780 device package.
(2) Not available for F780 and F1152 device packages.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
8–2:
Figure 8–2
Table 8–1
supported in Arria II devices. You can design the LVDS I/Os as true LVDS input,
output buffers, or emulated LVDS output buffers, if the combination does not exceed
the maximum count. For example, there are a total of 56 LVDS pairs of I/Os in 780-pin
EP2AGX45 device row (refer to
■
■
■
■
28 true LVDS input buffers with R
56 LVDS input buffers of which 28 are true LVDS input buffers with R
28 requires external 100-Ω termination
28 true LVDS output buffers and 28 emulated LVDS output buffers
56 emulated LVDS output buffers
to
shows a high-level chip overview of the Arria II GZ devices.
Table 8–4
General Purpose
General Purpose
I/O and Memory
I/O and Memory
PLL
PLL
Interface
Interface
(1)
(2)
list the maximum number of row and column LVDS I/Os
(Logic Elements, DSP,
Embedded Memory,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Clock Networks)
FPGA Fabric
PLL
PLL
Table
PLL
PLL
8–1). You can design up to a maximum of either:
D
OCT and 28 true LVDS output buffers
General Purpose
General Purpose
I/O and Memory
I/O and Memory
Interface
Interface
PLL
PLL
(1)
(2)
December 2010 Altera Corporation
Locations of the I/O Banks
D
OCT and