EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 143

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–32. Clock Switchover with the clkswitch (Manual) Control for Arria II Devices
Note to
(1) To start a manual clock switchover event, both inclk0 and inclk1 must be running when the clkswitch signal goes high.
December 2010 Altera Corporation
Figure
5–32:
switchover between the frequencies of operation. You must choose the backup clock
frequency and set the m, n, c, and k counters accordingly so the VCO operates in the
recommended operating frequency range of 600 to 1,600 MHz. The ALTPLL
MegaWizard Plug-In Manager interface notifies you if a given combination of inclk0
and inclk1 frequencies cannot meet this requirement.
Figure 5–32
by the clkswitch signal. In this case, both clock sources are functional and inclk0 is
selected as the reference clock. The clkswitch signal goes high, which starts the
switchover sequence. On the falling edge of inclk0, the counter’s reference clock
(muxout) is gated off to prevent clock glitching. On the falling edge of inclk1, the
reference clock multiplexer switches from inclk0 to inclk1 as the PLL reference, and
the activeclock signal changes to indicate which clock is currently feeding the PLL.
In automatic switchover with manual overide mode, the activeclock signal mirrors
the clkswitch signal. As both clocks are still functional during the manual switch,
neither clkbad signal goes high. Because the switchover circuit is positive-edge
sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch
back from inclk1 to inclk0. When the clkswitch signal goes high again, the process
repeats. The clkswitch signal and automatic switch only work if the clock being
switched to is available. If the clock is not available, the state machine waits until the
clock is available.
activeclock
clkswitch
clkbad0
clkbad1
muxout
inclk0
inclk1
shows an example waveform of the switchover feature when controlled
Arria II Device Handbook Volume 1: Device Interfaces and Integration
(Note 1)
5–39