EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 512

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–22
Table 2–5. Receiver Datapath Clock Frequencies in Non-Bonded Functional Modes with Rate Matcher for Arria II
Devices
Arria II Device Handbook Volume 2: Transceivers
Note to
(1) 250 MHz when you enable the PCIe hard IP.
Functional Mode
PCIe ×1 (Gen 1)
PCIe ×1 (Gen 2)
Serial RapidIO
Table
GIGE
2–5:
In non-bonded configurations with rate matcher, the CDR in each receiver channel
recovers the serial clock from the received data. Also, the serial recovered clock
frequency is half the configured data rate due to the half rate CDR architecture. The
serial recovered clock is divided within the receiver PMA to generate the parallel
recovered clock. The deserializer uses the serial recovered clock in the receiver PMA.
The parallel recovered clock and deserialized data is forwarded to the receiver PCS.
The parallel recovered clock from the receiver PMA in each channel clocks the word
aligner and the write port of the rate match FIFO. The low-speed parallel clock from
the transmitter local clock divider block in each channel clocks the read port of the
rate match FIFO, the 8B/10B decoder, and the write port of the byte deserializer (if
enabled). The parallel transmitter PCS clock or its divide-by-two version (if byte
deserializer is enabled) clocks the write port of the receiver phase compensation FIFO.
It is also driven on the tx_clkout port as the FPGA fabric-transceiver interface clock.
You can use the tx_clkout signal to latch the receiver data and status signals in the
FPGA fabric.
Table 2–5
modes with rate matcher.
Bonded Channel Configurations
Arria II GX and GZ devices support ×4 channel bonding that allows bonding of four
channels within the same transceiver block. It also supports ×8 channel bonding that
allows bonding of eight channels across two transceiver blocks in PCIe mode.
×4 Bonded Channel Configuration
The following functional modes support ×4 receiver channel bonded configuration:
■
■
■
In ×4 bonded channel configurations, the receiver datapath clocking varies,
depending on whether the configured functional mode uses the deskew FIFO or not.
PCIe ×4
XAUI
Basic ×4
3.125 Gbps
1.25 Gbps
1.25 Gbps
Data Rate
2.5 Gbps
2.5 Gbps
5 Gbps
lists the receiver datapath clock frequencies in non-bonded functional
1.5625 GHz
Recovered
Frequency
1.25 GHz
1.25 GHz
625 MHz
625 MHz
2.5 GHz
Serial
Clock
Recovered
Frequency
Parallel
Clock
(MHz)
312.5
250
500
125
125
250
Chapter 2: Transceiver Clocking in Arria II Devices
Serializer (MHz)
FPGA Fabric-Transceiver Interface
Without Byte
250
Transceiver Channel Datapath Clocking
125
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December 2010 Altera Corporation
(1)
Clock Frequency
Serializer (MHz)
With Byte
156.25
62.5
125
250
125
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