EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 275

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
December 2010 Altera Corporation
1
Using Both Center PLLs
You can use both center PLLs simultaneously to drive DPA-disabled channels on
upper and lower I/O banks. Unlike DPA-enabled channels, the center PLLs can drive
DPA-disabled channels cross-banks. For example, the upper center PLL can drive the
lower I/O bank at the same time the lower center PLL is driving the upper I/O bank,
and vice versa, as shown in
Center PLLs are available at the right I/O banks of Arria II GX devices and the right
and left I/O banks of Arria II GZ devices.
Figure 8–29. Both Center PLLs Driving Cross-Bank DPA-Disabled Channels Simultaneously
Figure
8–29.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
Reference
Reference
Center
Center
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
CLK
CLK
PLL
PLL
8–35