EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 261

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
PLLs
PLLs
LVDS and DPA Clock Networks
Figure 8–17. LVDS and DPA Clock Networks in the Arria II GX Devices without Center PLLs
December 2010 Altera Corporation
f
clock networks on the
left side of the device
No LVDS and DPA
The Arria II GX devices contain up to six PLLs with up to four center and corner PLLs
located on the right side of the device. Use the center/corner PLL on the right side of
the device to generate parallel clocks (rx_outclock and tx_outclock) and high-speed
clocks (diffioclk) for the SERDES and DPA circuitry.
the locations of the PLLs for Arria II GX devices. Clock switchover and dynamic
reconfiguration are allowed using the center/corner PLLs in high-speed differential
I/O support mode.
The Arria II GZ devices contain up to four left and right PLLs with up to two PLLs
located on the left side and two on the right side of the device. The left PLLs can
support high-speed differential I/O banks on the left side; the right PLLs can support
high-speed differential I/O banks on the right side of the device. The high-speed
differential I/O receiver and transmitter channels use these left and right PLLs to
generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks
(diffioclk).
Arria II GZ devices. The PLL VCO operates at the clock frequency of the data rate.
Clock switchover and dynamic reconfiguration are allowed using the left and right
PLL in high-speed differential I/O support mode.
For more information about PLLs, refer to the
Devices
The Arria II GX devices only have LVDS and DPA clock networks on the right side of
the device. The center/corner PLLs feed into the differential transmitter and receiver
channels through the LVDS and DPA clock networks.
show the LVDS clock tree for family members without center PLLs and with center
PLLs, respectively. The center PLLs can drive the LVDS clock tree above and below
them. In Arria II GX devices with or without center PLLs, the corner PLLs can drive
both top and bottom LVDS clock tree.
chapter.
Figure 8–2 on page 8–4
Quadrant
Quadrant
Quadrant
Quadrant
Arria II Device Handbook Volume 1: Device Interfaces and Integration
shows the locations of the left and right PLLs for
Clock Network and PLLs in Arria II
Clock
DPA
Corner
Corner
PLL
PLL
Figure 8–17
Figure 8–1 on page 8–3
LVDS
Clock
4
8
4
4
4
and
Figure 8–18
shows
8–21