EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 208

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–12
Figure 7–9. Number of DQ/DQS Groups per Bank in EP2AGX95 and EP2AGX125 Devices in the 1152-Pin FineLine BGA
Package
Notes to
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a × 4 DQ/DQS group with any of their pin members used for
Arria II Device Handbook Volume 1: Device Interfaces and Integration
configuration purposes. Ensure that the DQ/DQS groups you chose are not also used for configuration.
Figure
(Note 1)
7–9:
Figure 7–9
and EP2AGX125 devices in the 1152-pin FineLine BGA package.
74 User I/Os
70 User I/Os
I/O Bank 8A
I/O Bank 3A
×16/×18=2
×32/×36=1
×16/×18=2
×32/×36=1
×8/×9=4
×8/×9=4
×4=8
×4=8
EP2AGX95 and EP2AGX125 Devices
shows the number of DQ/DQS groups per bank in Arria II GX EP2AGX95
in the 1152-Pin FineLine BGA
70 User I/Os
74 User I/Os
I/O Bank 7A
I/O Bank 4A
×16/×18=2
×32/×36=1
×16/×18=2
×32/×36=1
×8/×9=4
×8/×9=4
×4=8
×4=8
16 User I/Os
16 User I/Os
I/O Bank 7B
I/O Bank 4B
×16/×18=0
×32/×36=0
×16/×18=0
×32/×36=0
×8/×9=1
×8/×9=1
×4=2
×4=2
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
I/O Bank 6A (2)
66 User I/Os
I/O Bank 5A
66 User I/Os
×16/×18=2
×32/×36=1
×16/×18=2
×32/×36=1
×8/×9=4
×8/×9=4
×4=8
×4=8
December 2010 Altera Corporation