EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 516

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–26
Table 2–7. Receiver Datapath Clock Frequencies in ×4 Bonded Functional Modes Without Deskew FIFO for Arria II
Devices
Arria II Device Handbook Volume 2: Transceivers
PCIe ×4 (Gen 2)
Notes to
(1) 250 MHz when you enable the PCIe hard IP.
(2) Arria II GZ devices only.
Functional Mode
PCIe ×4 (Gen 1)
Table
2–7:
(2)
In ×4 bonded channel configurations without deskew FIFO, the CDR in each receiver
channel recovers the serial clock from the received data. The serial recovered clock
frequency is half the configured data rate due to the half-rate CDR architecture. The
serial recovered clock is divided within each channel’s receiver PMA to generate the
parallel recovered clock. The deserializer uses the serial recovered clock in the
receiver PMA. The parallel recovered clock and deserialized data is forwarded to the
receiver PCS in each channel.
The parallel recovered clock from the receiver PMA in each channel clocks the word
aligner and write side of the rate match FIFO in that channel. The low-speed parallel
clock from the CMU0 clock divider block in the CMU0 Channel clocks the read port of the
rate match FIFO, the 8B/10B decoder, and the write port of the byte deserializer (if
enabled). The low-speed parallel clock or its divide-by-two version (if byte
deserializer is enabled) clocks the receiver phase compensation FIFO. It is also driven
on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the
coreclkout signal to latch the receiver data and status signals in the FPGA fabric for
all four bonded channels.
In ×4 bonded channel configurations, the receiver phase compensation FIFOs in all
four bonded channels share common read and write pointers and enable signals
generated in the CMU0 channel of the transceiver block.
Table 2–7
without deskew FIFO.
×8 Bonded Channel Configuration
PCIe ×8 and Basic ×8 functional mode supports ×8 receiver channel bonding
configurations. The eight bonded channels are located in two transceiver blocks,
referred to as the master transceiver block and slave transceiver block, with four
channels each.
Data Rate
(Gbps)
2.5
5
lists the receiver datapath clock frequencies in ×4 bonded functional modes
Recovered
Frequency
Serial
Clock
(GHz)
1.25
2.5
Transmitter PCS Clock
Parallel Recovered
Clock and Parallel
Frequency (MHz)
250
500
Chapter 2: Transceiver Clocking in Arria II Devices
Serializer (MHz)
FPGA Fabric-Transceiver Interface
Without Byte
250
Transceiver Channel Datapath Clocking
—
December 2010 Altera Corporation
(1)
Clock Frequency
Serializer (MHz)
With Byte
125
250