EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 58

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–12
Figure 3–11. Timing Waveform for Read-Write Operations for MLABs (Single-Port Mode
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Simple Dual-Port Mode
q_a (asynch)
address_a
Figure 3–11
mode with unregistered outputs for the MLAB. The rising clock edges trigger the read
operation whereas the falling clock edges triggers the write operation.
data_a
All memory blocks support simple dual-port mode. Simple dual-port mode allows
you to perform one-read and one-write operation to different locations at the same
time. The write operation occurs on port A; the read operation occurs on port B.
Figure 3–12
input and output clock mode in addition to the read and write clock mode.
Figure 3–12. Arria II Simple Dual-Port Memory
Note to
(1) Only available for Arria II GZ devices.
wrena
rdena
clk_a
Figure
3–12:
shows the timing waveforms for read and write operations in single-port
shows a simple dual-port configuration. Simple dual-port RAM supports
(old data)
A
a0
A
a0
B
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
C
B
C
(old data)
D
a1
rd_addressstall
ecc_status (1)
rdaddress[ ]
rdclocken
a1
E
rdclock
D
Chapter 3: Memory Blocks in Arria II Devices
rden
q[ ]
)
December 2010 Altera Corporation
F
E
Memory Modes