EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 411

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
Table 1–7. DC-Coupled Settings for Arria II Devices (Part 2 of 2)
December 2010 Altera Corporation
LVDS transmitter to Arria II GX and GZ receiver
Note to
(1) The differential OCT setting for Arria II GX and GZ transmitters and receivers is 85  (for Arria II GZ only) or 100 , except for the LVDS
transmitter settings, which do not have OCT set on the transmitter (as shown in
Table
1–7:
f
1
1
Programmable Equalization, DC Gain, and Offset Cancellation
Each Arria II GX and GZ receiver input buffer has independently programmable
equalization circuitry that boosts the high-frequency gain of the incoming signal,
thereby compensating for the low-pass filter effects of the physical medium. The
amount of high-frequency gain required depends on the loss characteristics of the
physical medium. Arria II GX and GZ equalization circuitry supports equalization
settings that provide up to 7 dB (Arria II GX) and 16 dB (Arria II GZ) of
high-frequency boost.
The Arria II GX and GZ receiver input buffer also supports programmable DC gain
circuitry. Unlike equalization circuitry, DC gain circuitry provides equal boost to the
incoming signal across the frequency spectrum.
You can select the proper equalization and DC gain settings in the ALTGX
MegaWizard Plug-In Manager. The receiver buffer supports DC gain settings of 0 dB,
3 dB, and 6 dB for Arria II GX devices and up to 12 dB for Arria II GZ devices.
This offset cancellation block cancels offset voltages between the positive and
negative differential signals within the equalizer stages in order to reduce the
minimum V
cancellation.
The offset cancellation for the receiver channels option is automatically enabled in
both the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers for
Receiver, Transmitter, and Receiver only configurations. When offset cancellation is
automatically enabled, you must instantiate the dynamic reconfiguration controller to
connect the reconfiguration ports created by the ALTGX MegaWizard Plug-In
Manager.
For more information about offset cancellation, refer to
Reconfiguration in Arria II
cancellation feature, refer to the
chapter.
Signal Threshold Detection Circuitry
Signal threshold detection circuitry has a hysteresis response that filters out any
high-frequency ringing caused by ISI effects or high-frequency losses in the
transmission medium. If the signal threshold detection circuitry senses the signal
level present at the receiver input buffer to be higher than the signal detect threshold,
it asserts the rx_signaldetect signal high. Otherwise, the rx_signaldetect signal is
held low.
Link
ID
requirement. The receiver input buffer and receiver CDR require offset
Devices. For the transceiver reset sequence with the offset
Reset Control and Power Down in Arria II Devices
(Note 1)
Figure
Transceiver Settings
1–27).
TX VCM (V)
Arria II Device Handbook Volume 2: Transceivers
—
AN 558: Implementing Dynamic
Receiver Settings
RX VCM (V)
1.1
1–25