EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 62

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–16
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Table 3–7
dual-port mode.
Table 3–7. M9K Block Mixed-Width Configuration (True-Dual Port Mode)
Table 3–8
dual-port mode.
Table 3–8. M144K Block Mixed-Width Configurations (True Dual-Port Mode)
In true dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output “new data” at that location or “old data”.
In true dual-port mode, you can access any memory location at any time from either
port. When accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens when you attempt to write to the
same address location from both ports at the same time. This results in unknown data
being stored to that address location. Conflict resolution circuitry is not built into the
Arria II memory blocks. You must handle address conflicts external to the RAM block.
16K × 8
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
1K × 9
512 × 18
8K × 16
4K × 32
16K × 9
8K × 18
4K × 36
Read Port
Read Port
lists the possible M9K block mixed-port width configurations in true
lists the possible M144K block mixed-port width configurations in true
8K × 1
v
v
v
v
v
—
—
16K × 8
v
v
v
—
—
—
4K × 2
v
v
v
v
v
—
—
8K × 16
v
v
v
—
—
—
2K × 4
v
v
v
v
v
—
—
4K × 32
v
v
v
—
—
—
Write Port
Write Port
1K × 8
Chapter 3: Memory Blocks in Arria II Devices
v
v
v
v
v
—
—
16K × 9
—
—
—
v
v
v
December 2010 Altera Corporation
512 × 16 1K × 9 512 × 18
v
v
v
v
v
—
—
8K × 18
v
v
v
—
—
—
—
—
—
—
—
v
v
Memory Modes
4K × 36
v
v
v
—
—
—
—
—
—
—
—
v
v