EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 537

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
1
Bonded Channel Configuration
All bonded transceiver channel configurations have a rate matcher in the receiver
data path.
In the ×4 bonded channel configurations, the Quartus II software automatically drives
the read port of the receiver phase compensation FIFO in all four channels with the
coreclkout signal. Use the coreclkout signal to latch the receiver data and status
signals from all four channels in the FPGA fabric.
In ×8 bonded channel configurations, the Quartus II software automatically drives the
read port of the receiver phase compensation FIFO in all eight channels with the
coreclkout signal from the master transceiver block. Use the coreclkout signal to
latch the receiver data and status signals from all eight channels in the FPGA fabric.
This configuration uses one FPGA global or regional clock resource per bonded link
for the coreclkout signal.
Arria II Device Handbook Volume 2: Transceivers
2–47