EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 453

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
December 2010 Altera Corporation
1
1
Figure 1–64. Transmitter Buffer Electrical Idle State
Receiver Detection
During the detect substate of the LTSSM state machine, the PCIe protocol requires the
transmitter channel to perform a receiver detect sequence to detect if a receiver is
present at the far end of each lane. The PCIe specification requires that a receiver
detect operation be performed during the P1 power state where the transmitter
output buffer is in electrical idle (tri-stated).
This feature requires the transmitter output buffer to be tri-stated (in electrical idle
mode), have OCT utilization, and run at 125 MHz on the fixedclk signal. You can
enable this feature in PCIe functional mode by setting the tx_forceelecidle and
tx_detectrxloopback ports to 1'b1.
When the tx_detectrxloopback signal is asserted high in the P1 power state, the PIPE
interface block sends a command signal to the transmitter buffer in that channel to
initiate a receiver detect sequence. On receiving this command signal, the receiver
detect circuitry creates a step voltage at the transmitter output buffer common mode
voltage. If an active receiver (that complies with the PCIe input impedance
requirements) is present at the far end, the time constant of the step voltage on the
trace is higher compared to when the receiver is not present. The receiver-detect
circuitry monitors the time constant of the step signal seen on the trace to decide if a
receiver was detected or not.
If a far-end receiver is successfully detected, the PIPE interface block asserts the
pipephydonestatus signal for one clock cycle and synchronously drives the
pipestatus[2:0] signal to 3'b011. If a far-end receiver is not detected, the PIPE
interface block asserts the pipephydonestatus signal for one clock cycle and
synchronously drives the pipestatus[2:0] signal to 3'b000.
There is some latency after asserting the tx_detectrxloopback signal before receiver
detection is indicated on the pipephydonestatus port. In addition, the
tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to the
tx_detectrxloopback port to ensure that the transmitter buffer is tri-stated.
For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the
serial link and the receiver termination values used in your system must be compliant
to the PCIe Base Specification 2.0. Receiver detect circuitry communicates the status of
the receiver detect operation to the PIPE interface block.
tx_forcelecidle
tx_dataout
T1
>20 ns
Arria II Device Handbook Volume 2: Transceivers
1–67