EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 25

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Overview for the Arria II Device Family
Arria II Device Architecture
Table 1–8. Location of OCT Calibration Block in Arria II Devices
December 2010 Altera Corporation
Arria II GX
Arria II GZ
Device
High-Speed LVDS I/O and DPA
Clock Management
All pin packages
780-pin flip chip FBGA
1152-pin flip chip FBGA
1517-pin flip chip FBGA
Package Option
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Arria II GX devices have dedicated configuration banks at Bank 3C and 8C, which
support dedicated configuration pins and some of the dual-purpose pins with a
configuration scheme at 1.8, 2.5, 3.0, and 3.3 V. For Arria II GZ devices, the
dedicated configuration pins are located in Bank 1A and Bank 1C. However, these
banks are not dedicated configuration banks; therefore, user I/O pins are available
in Bank 1A and Bank 1C.
Dedicated VCCIO, VREF, and VCCPD pin per I/O bank to allow voltage-referenced
I/O standards. Each I/O bank can operate at independent V
levels.
Dedicated circuitry for implementing LVDS interfaces at speeds from 150 Mbps to
1.25 Gbps
R
DPA circuitry and soft-CDR circuitry at the receiver automatically compensates for
channel-to-channel and channel-to-clock skew in source-synchronous interfaces
and allows for implementation of asynchronous serial interfaces with embedded
clocks at up to 1.25 Gbps data rate (SGMII and GbE)
Emulated LVDS output buffers use two single-ended output buffers with an
external resistor network to support LVDS, mini-LVDS, BLVDS (only for
Arria II GZ devices), and RSDS standards.
Provides dedicated global clock networks (GCLKs), regional clock networks
(RCLKs), and periphery clock networks (PCLKs) that are organized into a
hierarchical structure that provides up to 192 unique clock domains
Up to eight PLLs with 10 outputs per PLL to provide robust clock management
and synthesis
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FPGA fabric can use the unused transceiver PLLs to provide more flexibility
D
OCT for high-speed LVDS interfacing
Independently programmable PLL outputs, creating a unique and
customizable clock frequency with no fixed relation to any other clock
Inherent jitter filtration and fine granularity control over multiply and divide
ratios
Supports spread-spectrum input clocking and counter cascading with PLL
input clock frequencies ranging from 5 to 500 MHz to support both low-cost
and high-end clock performance
Bank 3C, Bank 7B, and Bank 8C
Bank 3A, Bank 4A, Bank 7A, and Bank 8A
Bank 1A, Bank 3A, Bank 4A, Bank 6A, Bank 7A, and Bank 8A
Bank 1A, Bank 2A, Bank 3A, Bank 4A, Bank 5A, Bank 6A, Bank 7A, and Bank 8A
Arria II Device Handbook Volume 1: Device Interfaces and Integration
i/O Bank
CCIO
, V
REF
, and V
CCPD
1–11