EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 113

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Table 5–2. Clock Input Pin Connectivity to GCLK Networks for Arria II GX Devices
Table 5–3. Clock Input Pin Connectivity to the GCLK Networks for Arria II GZ Devices
December 2010 Altera Corporation
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
Note to
(1) GCLK[0..3] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX device.
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
Clock Resources
Clock Resources
Table
5–2:
(1)
1
Dedicated Clock Inputs Pins
CLK pins can either be differential clocks or single-ended clocks. Arria II GX devices
support six differential clock inputs or 12 single-ended clock inputs, while Arria II GZ
devices support 16 differential clock inputs or 32 single-ended clock inputs. You can
also use the dedicated clock input pins CLK[4..15] (for Arria II GX devices) and
CLK[15..0] (for Arria II GZ devices) for high fan-out control signals such as
asynchronous clears, presets, and clock enables for protocol signals such as TRDY and
IRDY for PCI Express
Logic Array Blocks
You can drive up to four signals into each GCLK and RCLK network with logic array
block (LAB)-routing to allow internal logic to drive a high fan-out, low-skew signal.
You cannot drive Arria II PLLs by internally generated GCLKs or RCLKs. The input
clock to the PLL has to come from dedicated clock input pins or PLL-fed
GCLKs/RCLKs only.
PLL Clock Outputs
Table 5–2
and GCLKs.
—
—
—
v
4
—
—
—
v
0
—
—
—
1
v
—
—
—
v
5
and
—
—
—
v
2
Table 5–3
—
—
—
6
v
—
—
—
3
v
®
(PCIe
—
—
—
7
v
—
—
—
v
4
list the connection between the dedicated clock input pins
®
—
—
—
) through GCLK or RCLK networks.
v
5
—
—
—
8
v
—
—
—
v
6
CLK (p/n Pins)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
—
—
—
CLK (p/n Pins)
9
v
—
—
—
v
7
10
—
—
—
v
—
—
—
8
v
—
—
—
v
9
11
—
—
—
v
10
—
—
—
v
12
—
—
—
v
11
—
—
—
v
13
—
—
—
12
—
—
—
v
v
13
—
—
—
v
14
—
—
—
v
14
—
—
—
v
15
—
—
—
v
5–9
15
—
—
—
v