EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 126

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–22
Figure 5–17. External Clock Outputs for Arria II GX PLLs
Notes to
(1) You can feed these clock output pins with any one of the C[6..0],or m counters.
(2) The PLL<#>_CLKOUT<#>p and PLL<#>_CLKOUT<#>n pins can be either single-ended or pseudo-differential clock outputs. The Arria II GX PLL
(3) These external clock enable signals are available only when you use the ALTCLKCTRL megafunction.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
only routes single-ended I/Os to PLL<#>CLKOUT<#>p pins, while you can use PLL<#>_CLKOUT<#>n pins as user I/Os.
Figure
5–17:
Figure 5–17
For Arria II GX devices, any of the output counters (C[6..0]) or the M counter can feed
the dedicated external clock outputs, as shown in
or frequency can drive all the output pins available from a given PLL.
For Arria II GZ devices, each top and bottom PLL supports six clock I/O pins,
organized as three pairs of pins:
■
■
■
1st pair—two single-ended I/O or one differential I/O
2nd pair—two single-ended I/O or one differential external feedback input
(FBp/FBn)
3rd pair—two single-ended I/O or one differential input
Arria II GX
PLLs
shows the clock I/O pins associated with Arria II GX PLLs.
C0
C1
C2
C3
C4
C5
C6
m
Internal Logic
PLL<#>_CLKOUT<#>p (1), (2)
clkena1 (3)
clkena0 (3)
PLL<#>_CLKOUT<#>n (1), (2)
Chapter 5: Clock Networks and PLLs in Arria II Devices
Figure
5–17. Therefore, one counter
December 2010 Altera Corporation
PLLs in Arria II Devices