EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 223

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
December 2010 Altera Corporation
1
1
DLL
DQS phase-shift circuitry uses a DLL to dynamically control the clock delay required
by the DQS/CQ and CQn pins. The DLL, in turn, uses a frequency reference to
dynamically generate control signals for the delay chains in each of the DQS/CQ and
CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are
Gray-coded to reduce jitter when the DLL updates the settings. Phase-shift circuitry
requires a maximum of 1,280 clock cycles to lock and calculate the correct input clock
period when the DLL is in low jitter mode. Otherwise, only 256 clock cycles are
required. Do not send data during these clock cycles because there is no guarantee
that the data is properly captured. As the settings from the DLL may not be stable
until this lock period has elapsed, be aware that anything with these settings may be
unstable during this period.
You can still use the DQS phase-shift circuitry for any memory interfaces that are
operating at less than 100 MHz. However, the DQS signal may not shift over 2.5 ns. At
less than 100 MHz, while the DQS phase shift may not be exactly centered to the data
valid window, sufficient margin must still exist for reliable operation.
There are two DLLs in an Arria II GX device and four DLLs in Arria II GZ device,
located in the top-left and bottom-right corners of the Arria II GX device and each
corner of the Arria II GZ device. These DLLs can support a maximum of two unique
frequencies (Arria II GX devices) or four unique frequencies (Arria II GZ devices),
with each DLL running at one frequency. Each DLL can have two outputs with
different phase offsets, which allows one Arria II GX device to have four different
DLL phase shift settings and Arria II GZ device to have eight different DLL phase
shift settings.
For Arria II GX devices, each DLL can access the top, bottom, and right side of the
device. This means that each I/O bank is accessible by two DLLs, giving more
flexibility to create multiple frequencies and multiple-type interfaces. The DLL
outputs the same DQS delay settings for the different sides of the device.
For Arria II GZ devices, each DLL can access the two adjacent sides from its location
within the device. For example, DLL0 on the top left of the device can access the top
side (I/O banks 7A, 7B, 7C, 8A, 8B, and 8C) and the left side of the device (I/O banks
1A, 1B, 1C, 2A, 2B, and 2C). This means that each I/O bank is accessible by two DLLs,
giving more flexibility to create multiple frequencies and multiple-type interfaces.
You can have two different interfaces with the same frequency on the two sides
adjacent to a DLL, where the DLL controls the DQS delay settings for both interfaces.
Interfaces that span across two sides of the device are not recommended for
high-performance memory interface applications. However, Arria II GX devices
support split interfaces (top and bottom I/O banks) and interfaces with multiple
DQ/DQS groups wrapping over column and row I/Os from adjacent sides of the
devices. Interfaces spanning “top and bottom I/O banks”, “right and bottom I/O
banks”, or “top, bottom, and right I/O banks” are supported.
For Arria II GX devices, each bank can use settings from either one or both DLLs. For
example, DQS1R can get its phase-shift settings from DLL0, and DQS2R can get its
phase-shift settings from DLL1.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
7–27