EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 393

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Clock Multiplier Units (CMU)
Figure 1–4. Top-Level Diagram of CMU Block Connections in a Transceiver Block
Notes to
(1) Clocks provided to support bonded channel functional mode.
(2) For more information, refer to the
December 2010 Altera Corporation
Figure
1–4:
Transmitter Channel 2
Transmitter Channel 0
Transmitter Channel 2
Transmitter Channel 0
To Transmitter PMA
To Transmitter PMA
To Transmitter PMA
To Transmitter PMA
To Transmitter PCS
To Transmitter PCS
To Transmitter PCS
To Transmitter PCS
Input Reference Clock (2)
Input Reference Clock (2)
Input Reference Clock (2)
Input Reference Clock (2)
Transmitter Channel 3
Transmitter Channel 3
Transmitter Channel 1
Transmitter Channel 1
Figure 1–4
blocks and the transceiver channels.
Transceiver Clocking for Arria II Devices
shows a top-level block diagram of the connections between the CMU
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
High-Speed Serial Clock
High-Speed Serial Clock
High-Speed Serial Clock
High-Speed Serial Clock
CMU1 Block
CMU0 Block
CMU1 Block
CMU0 Block
CMU1 PLL High-Speed Clock
CMU0 PLL High-Speed Clock
High-Speed Serial Clock (1)
Low-Speed Parallel Clock (1)
CMU1 PLL High-Speed Clock
CMU0 PLL High-Speed Clock
High-Speed Serial Clock (1)
Low-Speed Parallel Clock (1)
Divider
Divider
Divider
Divider
Local
Local
Local
Local
Clock
Block
Clock
Block
Clock
Block
Clock
Block
Transceiver Block GXBL2
Transceiver Block GXBL1
chapter.
Arria II Device Handbook Volume 2: Transceivers
From GXBL3
From GXBL0
From GXBL3
To GXBL0
×1 Line
×1 Line
×4 Line
×N Line
×N Line
×1 Line
×1 Line
×4 Line
×N Line
×N Line
1–7