EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 454

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–68
Arria II Device Handbook Volume 2: Transceivers
1
Figure 1–65
successfully detected and where a receiver was not detected, respectively.
Figure 1–65. Receiver Detect Successful Operation
Figure 1–66. Receiver Detect Unsuccessful Operation
Compliance Pattern Transmission Support
The LTSSM state machine can enter the polling.compliance substate where the
transmitter must transmit a compliance pattern as specified in the PCIe Base
Specification 2.0. The polling.compliance substate is intended to assess if the
transmitter is electrically compliant with the PCIe voltage and timing specifications.
The compliance pattern is a repeating sequence of the following four code groups:
■
■
■
■
The PCIe protocol requires the first /K28.5/ code group of the compliance pattern to
be encoded with negative current disparity. To satisfy this requirement, the PIPE
interface block provides an input signal (tx_forcedispcompliance). A high level on
the tx_forcedispcompliance signal forces the associated parallel transmitter data on
the tx_datain port to transmit with a negative current running disparity.
For 8-bit transceiver channel width configurations, you must drive the
tx_forcedispcompliance signal high in the same parallel clock cycle as the first
/K28.5/ of the compliance pattern on the tx_datain port. For 16-bit transceiver
channel width configurations, you must drive only the LSB of the
tx_forcedispcompliance[1:0] signal high in the same parallel clock cycle as
/K28.5/D21.5/ of the compliance pattern on the tx_datain port.
/K28.5/
/D21.5/
/K28.5/
/D10.2/
and
Figure 1–66
tx_detectrxloopback
tx_detectrxloopback
pipephydonestatus
pipephydonestatus
powerdown[1:0]
powerdown[1:0]
pipestatus[2:0]
pipestatus[2:0]
show the receiver detect operation where a receiver was
3'b000
Chapter 1: Transceiver Architecture in Arria II Devices
2'b10(P1)
2'b10(P1)
3'b000
3'b011
December 2010 Altera Corporation
Functional Modes