EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 253

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Figure 8–9. DPA Clock Phase to Serial Data Timing Relationship
Note to
(1) T
December 2010 Altera Corporation
VCO
Figure
is defined as the PLL serial clock period.
8–9:
Figure 8–9
incoming serial data.
The DPA block requires a training pattern and sequence of at least 256 repetitions. The
training pattern is not fixed, so you can use any training pattern with at least one
transition. An optional user controlled signal (rx_dpll_hold) freezes the DPA clock on
its current phase when asserted. This signal is useful if you do not want the DPA
circuitry to continuously adjust the phase after initial phase selection.
The DPA circuitry loses lock when it switches phases to maintain an optimal sampling
phase. After it is locked, the DPA circuitry can lose the lock status under either of the
following conditions:
■
■
An independent reset signal (rx_reset) is routed from the FPGA fabric to reset the
DPA circuitry while in the user mode. The DPA circuitry must be retrained after reset.
Synchronizer
The synchronizer is a 1-bit wide and 6-bit deep FIFO buffer that compensates for the
phase difference between DPA_diffioclk and the high-speed clock (LVDS_diffioclk)
produced by the PLL. Because every DPA channel might have a different phase
selected to sample the data, you need the FIFO buffer to synchronize the data to the
high-speed LVDS clock domain. The synchronizer can only compensate for phase
differences, not frequency differences between the data and the input reference clock
of the receiver, and is automatically reset when the DPA circuitry first locks to the
incoming data.
An optional signal (rx_fifo_reset) is available to the FPGA fabric to reset the
synchronizer. Altera recommends using rx_fifo_reset to reset the synchronizer
when the DPA signal is in a loss-of-lock condition and the data checker indicates
corrupted received data.
rx_in
135˚
180˚
225˚
270˚
315˚
45˚
90˚
0˚
One phase change (adjacent to the current phase)
Two phase changes in the same direction
0.125T
shows the possible phase relationships between the DPA clocks and the
D0
vco
D1
T
D2
vco
Arria II Device Handbook Volume 1: Device Interfaces and Integration
D3
(Note 1)
D4
Dn
8–13