EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 322

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–42
Table 9–16. Dedicated Configuration Pins on the Arria II Device (Part 3 of 4)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
nCE
nCEO
ASDO
nCSO
DCLK
Pin Name
(2)
(2)
(2)
User Mode
N/A
N/A
N/A
N/A
I/O
Configuration
schemes (PS,
Synchronous
configuration
FPP, AS)
Scheme
AS
AS
All
All
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Output (AS)
open-drain
Input (PS,
Pin Type
Output
Output
Output
Input
FPP)
Active-low chip enable. The nCE pin activates the device with
a low signal to allow configuration. The nCE pin must be held
low during configuration, initialization, and user mode. In
single device configuration, it must be tied low. In
multi-device configuration, nCE of the first device is tied low
while its nCEO pin is connected to nCE of the next device in
the chain.
The nCE pin must also be held low for successful JTAG
programming of the device.
Output that drives low when device configuration is
complete. In a single-device configuration, this pin is left
floating. In a multi-device configuration, this pin feeds the
next device’s nCE pin and is pulled high by an external
10-k Ω resistor. The nCEO of the last device in the chain is
left floating.
The nCEO pin is powered by V
V
After configuration, nCEO is available as user I/O pins. The
state of the nCEO pin depends on the Dual-Purpose Pin
settings.
Control signal from the Arria II device to the serial
configuration device in AS mode used to read out
configuration data.
In AS mode, ASDO has an internal pull-up resistor that is
always active.
Output control signal from the Arria II device to the serial
configuration device in AS mode that enables the
configuration device.
In AS mode, nCSO has an internal pull-up resistor that is
always active.
In PS and FPP configurations, DCLK is the clock input used
to clock data from an external source into the target device.
Data is latched into the device on the rising edge of DCLK.
In AS mode, DCLK is an output from the Arria II device that
provides timing for the configuration interface. In AS mode,
DCLK has an internal pull-up resistor (typically 25 kΩ) that is
always active.
After configuration, this pin by default is driven into an
inactive state. In schemes that use a control host, DCLK must
be driven either high or low, whichever is more convenient.
Toggling this pin after configuration does not affect the
configured device.
CCPGM
for Arria II GZ devices.
Description
CCIO
December 2010 Altera Corporation
for Arria II GX devices and
Device Configuration Pins