EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 466

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–80
Arria II Device Handbook Volume 2: Transceivers
Figure 1–76
Figure 1–76. XAUI and XGMII Layers
The XGMII interface consists of four 8-bit lanes. At the transmit side of the XAUI
interface, the data and control characters are converted within the XGMII extender
sublayer (XGXS) into an 8B/10B encoded data stream. Each data stream is then
transmitted across a single differential pair running at 3.125 Gbps (3.75 Gbps for
HiGig/HiGig+). At the XAUI receiver, the incoming data is decoded and mapped
back to the 32-bit XGMII format. This provides a transparent extension of the physical
reach of the XGMII and also reduces the interface pin count.
XAUI functions as a self-managed interface because code group synchronization,
channel deskew, and clock domain decoupling are handled with no upper layer
support requirements. This functionality is based on the PCS code groups that are
used during the IPG time and idle periods.
Arria II GX and GZ transceivers configured in XAUI mode provide the following
protocol features:
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■
■
■
■
■
XGMII-to-PCS code conversion at the transmitter—The 8B/10B encoder in the
Arria II GX and GZ transmitter datapath is controlled by a transmitter state
machine that maps various 8-bit XGMII codes to 10-bit PCS code groups. This
state machine complies with the IEEE P802.3ae PCS transmit source state diagram.
PCS-to-XGMII code conversion at the receiver—The 8B/10B decoder in the
Arria II GX and GZ receiver datapath is controlled by a XAUI receiver state
machine that converts received PCS code groups into specific 8-bit XGMII codes.
8B/10B encoding and decoding
IEEE P802.3ae-compliant synchronization state machine
±100 PPM clock rate compensation
Channel deskew of four lanes of the XAUI link
OSI Reference
Model Layers
Presentation
Application
Transport
Data Link
Network
Physical
Session
shows the relationships between the XGMII and XAUI layers.
Access/Collision Detect (CSMA/CD) Layers
(XAUI)
LAN Carrier Sense Multiple
Physical Layer Device
MAC (Optional)
XGMII Extended
XGMII Extended
Reconcilation
Higher Layers
10 Gbps
Medium
Sublayer
Sublayer
Chapter 1: Transceiver Architecture in Arria II Devices
MAC
LLC
10 Gigibit Media Independent Interface
10 Gigibit Attachment Unit Interface
10 Gigibit Media Independent Interface
Medium Dependant Interface
December 2010 Altera Corporation
Functional Modes