EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 259

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Figure 8–15. Receiver Datapath in Soft CDR Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
December 2010 Altera Corporation
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
8–15:
10
Soft CDR Mode
Figure 8–15
PLL uses the local clock source as the reference clock. The reference clock must be a
differential signal. The DPA circuitry continuously changes its phase to track the parts
per million (ppm) difference between the upstream transmitter and the local receiver
reference input clocks. Use the DPA_diffioclk clock for bit-slip operation and
deserialization. The DPA_diffioclk clock is divided by the deserialization factor to
produce the rx_divfwdclk clock, which is then forwarded to the FPGA fabric. The
receiver output data (rx_out) to the FPGA fabric is synchronized to this clock. The
parallel clock rx_outclock, generated by the center/corner PLL, is also forwarded to
the FPGA fabric.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the soft CDR mode datapath block diagram. In soft CDR mode, the
IOE
2
PLL (4)
3
DOUT DIN
Multiplexer
Bit Slip
Clock
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
(Note
diffioclk
1), (2),
rx_inclock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
(3)
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
Data
DPA Clock
DPA Circuitry
DIN
+
LVDS Clock Domain
DPA Clock Domain
rx_in
8–19