EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 201

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Table 7–1. DQ/DQS Bus Mode Pins for Arria II Devices
December 2010 Altera Corporation
×4
×8/×9
×16/×18
×32/×36
×32/×36
Notes to
(1) The QVLD pin is not used in the ALTMEMPHY megafunction and it is only applicable for Arria II GZ devices.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
(3) Two ×4 DQ/DQS groups are stitched to make a ×8/×9 group so there are a total of 12 pins in this group.
(4) Four ×4 DQ/DQS groups are stitched to make a ×16/×18 group.
(5) Eight ×4 DQ/DQS groups are stitched to make a ×32/×36 group.
(6) The DM pin can be supported if differential DQS is not used and the group does not have additional signals.
(7) These ×32/×36 DQ/DQS groups are available in EP2AGZ300 and EP2AGZ350 devices in 1152- and 1517-pin FineLine BGA packages. There are
(8) There are 40 pins in each of these DQ/DQS groups. You cannot place the BWSn pins within the same DQ/DQS group as the write data pins
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQ/DQS group in a particular device. Check the pin table for the exact number per group. For DDR3, DDR2,
and DDR interfaces, the number of pins is further reduced for an interface larger than ×8 due to the need of one DQS pin for each ×8/×9 group
that is used to form the x16/×18 and ×32/×36 groups.
40 pins in each of these DQ/DQS groups.
because of insufficient pins availability.
Mode
(3)
Table
(4)
(5)
(7)
7–1:
DQSn Support
The DQ and DQS pin locations are fixed in the pin table. Memory interface circuitry is
available in every Arria II I/O bank that does not support transceivers. All memory
interface pins support the I/O standards required to support DDR3, DDR2,
DDR SDRAM, QDR II+ and QDR II SRAM, and RLDRAM II devices.
Arria II devices support DQ and DQS signals with DQ bus modes of ×4, ×8/×9,
×16/×18, or ×32/×36, although not all devices support DQS bus mode in ×32/×36.
The DDR, DDR2, and DDR3 SDRAM interfaces use one DQS pin for each ×8 group;
for example, an interface with a ×72 wide interface requires nine DQS pins. When any
of these pins are not used for memory interfacing, you can use these pins as user I/Os.
Additionally, you can use any DQSn or CQn pins not used for clocking as DQ (data)
pins.
Table 7–1
DQSn/CQn pin pair, for Arria II devices.
Yes
Yes
Yes
Yes
Yes
lists pin support per DQ/DQS bus mode, including the DQS/CQ and
CQn Support
Yes
Yes
Yes
Yes
No
Parity or DM
(Optional)
No
No
Yes
Yes
Yes
(6)
(8)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
(Optional)
QVLD
Yes
Yes
Yes
Yes
No
(1)
Data Pins per
Number of
16 or 18
32 or 36
32 or 36
Typical
Group
8 or 9
4
Data Pins per
Number of
Maximum
Group
11
23
47
39
5
(2)
7–5