EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 538
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Quantity
Price
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Part Number:
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Manufacturer:
ALTERA
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Part Number:
EP2AGX45DF29I5N
Manufacturer:
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Quantity:
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- EP2AGX45CU17C6N PDF datasheet
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2–48
Figure 2–27. FGPA Fabric-Receiver Interface Clocking in an ×4 Bonded Channel Configuration
Arria II Device Handbook Volume 2: Transceivers
Channel 3
Channel 2
Channel 1
Channel 0
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Low-Speed Parallel Clock
Low-Speed Parallel Clock
CMU1 Block
CMU0 Block
Low-Speed Parallel Clock
Low-Speed Parallel Clock
from CMU0 Clock Divider
from CMU0 Clock Divider
from CMU0 Clock Divider
from CMU0 Clock Divider
Figure 2–27
configuration.
Parallel Data
Parallel Data
Parallel Data
Parallel Data
Divider
CMU0
Clock
/2
/2
/2
/2
shows FPGA fabric-receiver interface clocking in an ×4 bonded channel
CMU1
CMU0
PLL
PLL
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
RX Phase
RX Phase
RX Phase
RX Phase
Reference Clock
/2
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
coreclkout
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
FPGA Fabric
December 2010 Altera Corporation
rx_coreclk[3]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
and Status
and Status
and Status
and Status
Channel 3
Channel 2
Channel 1
Channel 0
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
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