EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet
EP2AGX45DF29I5N
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Volume 3: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-4.0 Arria II Device Handbook Document last updated for Altera Complete Design Suite version: Document publication date: 10.1 December 2010 ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Auto-Calibrating External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Connecting a Serial Configuration Device to an Arria II Device Family on AS Interface . . . . . . . . . . . 2–1 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 December 2010 Altera Corporation Arria II Device Handbook Volume 3: Device Datasheet and Addendum ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Contents December 2010 Altera Corporation ...
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... Chapter 1. Device Datasheet for Arria II Devices Revised: Part Number: AIIGX53001-4.0 Chapter 2. Addendum for the Arria II Device Handbook Revised: Part Number: AIIGX53002-2.0 December 2010 Altera Corporation December 2010 December 2010 Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter Revision Dates ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter Revision Dates December 2010 Altera Corporation ...
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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. December 2010 Altera Corporation Section I. Device Datasheet and Addendum for Arria II Devices ® ...
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... I–2 Arria II Device Handbook Volume 3: Device Datasheet and Addendum Section I: Device Datasheet and Addendum for Arria II Devices December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... V — 1.21 V — 1.8 V –55 125 °C –65 150 °C Minimum Maximum Unit -0.5 1.35 V -0.5 1.8 V -0.5 3.75 V -0.5 3.75 V -0.5 3.75 V -0.5 3.75 V -0.5 3.9 V -0.5 3.75 V -0.5 1.35 V -0.5 3.75 V -0.5 4 December 2010 Altera Corporation ...
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... A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.3 V can only be at 4.3 V for 5.41% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 5.41/10ths of a year. December 2010 Altera Corporation Description Arria II Device Handbook Volume 3: Device Datasheet and Addendum 1– ...
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... I/O Standard Chapter 1: Device Datasheet for Arria II Devices Electrical Characteristics Overshoot Duration Unit High Time 100.000 % 79.330 % 46.270 % 27.030 % 15.800 % 9.240 % 5.410 % 3.160 % 1.850 % 1.080 % 0.630 % 0.370 % 0.220 % I/O Frequency (MHz) 333 400 333 260 250 200 December 2010 Altera Corporation ...
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... Supplies power to the transceiver PMA V CCA regulator Supplies power to the transceiver PMA TX, V CCL_GXB PMA RX, and clocking Supplies power to the transceiver PMA V CCH_GXB output (TX) buffer T Operating junction temperature J December 2010 Altera Corporation . RAMP Condition Minimum — 0.87 — 1.425 — 1.2 — 3.135 — 2.85 — ...
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... Power Supply Ramp time RAMP Notes to Table 1–5: (1) For more information about supply pin connections, refer to the (2) Altera recommends a 3.0-V nominal battery voltage when connecting V security key, you may connect the V CCBAT (3) V must be 2.5-V for I/O banks with 2.5-V and lower V CCPD (4) V for 3C and 8C I/O banks where the configuration pins reside only supports 3 ...
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... T Operating junction temperature J t Power supply ramp time RAMP Notes to Table 1–6: (1) Altera recommends a 3.0-V nominal battery voltage when connecting V security key, you may connect the V CCBAT (2) V must be 2.5 V when V is 2.5, 1.8, 1. CCPD CCIO ( (4) V must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR), or CCA_L/R both, are configured at a base data rate > ...
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... Min Max Min Max Min Max 50 — 70 — 70 — –50 — –70 — –70 — — 300 — 500 — 500 — –300 — –500 — –500 0.7 1.7 0.8 2 0.8 2 December 2010 Altera Corporation Unit µA µA µA µA V ...
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... S 1.5, 1.2 without calibration 50- R 50- series OCT S 1.5, 1.2 without calibration 25- 25- series OCT 3.0, 2.5, 1.8, 1.5, with calibration 1.2 December 2010 Altera Corporation V (V) CCIO 1.2 1.5 1.8 Max Min Max Min Max — 25.0 — ...
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... CCIO ± 10 1.5, 1 3.0, 2.5, CCIO ± 10 1.8, 1.5, 1 3.0, 2.5, CCIO ± 10 1.8, 1.5, 1.2 Electrical Characteristics (Note 1) Unit Industrial ± ± (Note 1) Unit C3,I3 C4,I4 ± 8 ± ± 8 ± ± 10 ± ± 10 ± ± 10 ± December 2010 Altera Corporation ...
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... Equation 1–1 voltage and temperature vary after power-up calibration for Arria II GX and GZ devices. Equation 1–1. OCT Variation Notes to Equation (1) R value calculated from OCT V . CCIO December 2010 Altera Corporation Resistance Tolerance Conditions (V) C3, 3.0, 2.5 ± 40 CCIO V = 1.8, 1.5 ± 40 CCIO ...
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... Description Chapter 1: Device Datasheet for Arria II Devices Electrical Characteristics at power up. CCIO dR/dV (%/mV) 0.035 0.039 0.086 0.136 0.288 (Note 1) dR/dV (%/mV) 0.0297 0.0344 0.0499 0.0744 0.1241 Typical Unit 7 pF December 2010 Altera Corporation ...
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... All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V December 2010 Altera Corporation Description Conditions ...
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... CCIO Electrical Characteristics Typ Max Unit 25 — k 25 — k 25 — k 25 — k 25 — k . (Note 1) Maximum 300 (2) 100 dv/dt, in which “C” is I/O pin IOPIN range for CCIO Minimum Unit 220 mV 180 mV 110 December 2010 Altera Corporation ...
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... LVTTL 2.85 3 3.15 LVCMOS 2.85 3 3.15 2.5 V 2.375 2.5 2.625 1.8 V 1.71 1.8 1.89 1.5 V 1.425 1.5 1.575 December 2010 Altera Corporation Table 1–35 list input voltage (V and V IH and and V values are valid at the corresponding Table 1–22 through V ( Min ...
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... REF V 0.04 0.04 CCIO REF REF 0.969 V REF 0.04 0.04 0.53 × 0.47 × 0.53 × V REF CCIO CCIO CCIO 0.95 — — CCIO 0.9 — — CCIO 0.53 × — — CCIO V CCIO December 2010 Altera Corporation I OH (mA) -2 -0.5 -0 ...
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... SSTL-2 Class I -0.3 0.15 V REF SSTL-2 Class II -0.3 0.15 V REF SSTL-18 Class I -0.3 0.125 V REF SSTL-18 Class II -0.3 0.125 V REF SSTL-15 Class I — 0.1 December 2010 Altera Corporation V (V) V (V) V IH(DC) IL(AC) IH(AC) Min Max Max - REF CCIO V - 0.35 REF 0.18 ...
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... Typ CCIO CCIO CCIO 0.62 — + 0.2 + 0 CCIO CCIO CCIO + 0.5 — + 0.6 - 0.125 0.175 V CCIO — 0.35 — — 2 December 2010 Altera Corporation I OH (mA) -16 -8 -16 -8 -16 -8 -16 (V) Max V /2 CCIO + 0. CCIO + 0.125 / — (V) Max V /2 CCIO + 0. CCIO + 0.125 / ...
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... V <= 1. range: 90 <= RL <= 110 (4) The RSDS and mini-LVDS I/O standards are only supported for differential outputs. (5) The LVPECL input standard is supported at the dedicated clock input pins (GCLK) only. December 2010 Altera Corporation V (V) V (V) DIF(DC) X(AC) Max Min ...
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... Mbps, the minimum input voltage is 0.85 V; the maximum input voltage is 1.75 V. For F MAX 0.45 V; the maximum input voltage is 1.95 V. Power Consumption for the Arria II Device Family Altera offers two ways to estimate power for a design: ■ Using the Microsoft Excel-based Early Power Estimator ■ ...
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For more information about power estimation tools, refer to the Power Analysis chapter in volume 3 of the Quartus II Handbook. Switching Characteristics This section provides performance characteristics of the Arria II GX and GZ core and periphery blocks ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices (Part Symbol/ Condition Description Min Duty cycle — 45 Peak-to-peak differential input — 200 voltage Spread-spectrum modulating clock PCIe 30 frequency Spread-spectrum PCIe — downspread –0.5% On-chip termination ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices (Part Symbol/ Condition Description Min Transceiver Clocks Calibration block clock frequency — 10 (cal_blk_clk) PCIe fixedclk clock Receiver — frequency Detect Dynamic 2.5/ reconfig_ reconfig. clk clock 37.5 ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices (Part Symbol/ Condition Description Min Maximum V = 0.82 V ICM — peak-to-peak setting differential input V =1.1 V voltage V (diff ICM — ID setting (3) p-p) ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices (Part Symbol/ Condition Description Min CDR LTR time — — (5) CDR minimum — 15 T1b (6) LTD lock time — 0 (7) Data lock time from rx_ ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices (Part Symbol/ Condition Description Min Return loss PCIe common mode Rise time (9) — 50 Fall time — 50 Intra- differential pair — — skew Intra-transceiver PCIe ×4 ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices (Part Symbol/ Condition Description Min Digital reset — pulse width Notes to Table 1–34: (1) For AC-coupled links, the on-chip biasing circuit is switched off before and during ...
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... MHz December 2010 Altera Corporation ...
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... DC gain = 0 dB input pins (14) Data Rate > 5 Gbps Equalization = 0 DC gain = 0.82 V ICM setting V ICM V = 1.1 V setting ICM Receiver DC Coupling Support December 2010 Altera Corporation –C3 and –I3 (1) Min Typ Max — 125 — 2.5/ 37.5 — 50 (2) — — — ...
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... UI — — — — 75 µs 15 — — µs — — 4000 ns — — 4000 ns MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz recon fig_ — — 17000 clk cycles December 2010 Altera Corporation ...
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... PCIe ×4, Basic ×4 ×8 PMA and PCS Inter-transceiver block bonded mode transmitter Example: PCIe ×8, channel-to-channel skew Basic ×8 CMU0 PLL and CMU1 PLL Supported Data Range December 2010 Altera Corporation –C3 and –I3 (1) Min Typ Max — 0 — — ...
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... Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics –C4 and –I4 Unit Min Typ Max s 1 s — — 100 MHz MHz MHz MHz MHz 3 - 5.5 MHz 3 - 5.5 MHz MHz MHz MHz 3 MHz 25 — 250 MHz December 2010 Altera Corporation ...
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... Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive the minimum eye opening requirement with Receiver Equalization enabled. (15) The rise and fall time transition is specified from 20% to 80%. December 2010 Altera Corporation –C3 and –I3 (1) ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum LTR LTD lock time CDR Minimum T1b LTR Invalid data Data lock time from rx_freqlocked Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics LTD Valid data LTD Valid data December 2010 Altera Corporation ...
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... Figure 1–4. Transmitter Output Waveform Single-Ended Waveform V CM Differential Waveform Table 1–36 lists the typical V Table 1–36. Typical V Symbol V differential OD peak-to-peak Typical (mV) December 2010 Altera Corporation (diff peak-peak (single-ended (diff peak-peak (single-ended for TX term that equals 85 . for Arria II GZ devices. ...
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... Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics V Setting (mV) OD 400 600 700 800 900 1000 1200 0.5 0.2 1.2 0.6 1.8 1.1 2.7 1.7 December 2010 Altera Corporation ...
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... N/A 19 N/A N/A 20 N/A N/A 21 N/A N/A 22 N/A N/A 23 N/A N/A 24 N/A N/A 25 N/A N/A 26 N/A N/A 27 N/A N/A 28 N/A N/A December 2010 Altera Corporation Table 1–39 Arria II HSSI HSPICE models. V Setting 0 0 0.7 0.3 0 1.2 0.5 0.3 1.3 0.8 0.5 1 ...
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... C5 Min Typ Max Min Typ Max — — 0.1 — — — — 0.01 — — 0.01 — — 0.1 — — — — 0.01 — — 0.01 > 15 > 15 > 1.5 > 1.5 > 0.15 > 0.15 December 2010 Altera Corporation Unit 0 0 ...
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... Fibre Channel Receiver Jitter Tolerance (3), Deterministic Pattern = jitter FC-1 CJTPAT Random jitter Pattern = FC-1 CJTPAT Fc/25000 Sinusoidal jitter FC-1 Fc/1667 Deterministic Pattern = jitter FC-2 CJTPAT December 2010 Altera Corporation (Note Typ Max Min Typ Max > 15 > 15 > 1.5 > 1.5 > 0.15 > 0.15 > 0.15 > 0.15 (10) — ...
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... December 2010 Altera Corporation Unit ...
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... Deterministic 3.125 Gbps jitter tolerance (peak-to-peak) Pattern = CJPAT Data Rate = Combined 1.25, 2.5, deterministic and 3.125 Gbps random jitter tolerance Pattern = (peak-to-peak) CJPAT December 2010 Altera Corporation (Note Typ Max Min Typ Max (6) — 0.17 — — 0.17 — 0.35 — ...
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... C5 Min Typ Max Min Typ Max > 8.5 > 8.5 > 0.1 > 0.1 > 0.1 > 0.1 — — 0.14 — — 0.14 — — 0.279 — — 0.279 > 0.4 > 0.4 > 0.66 > 0.66 — — — — — — December 2010 Altera Corporation Unit ...
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... Jitter frequency = 1.875MHz Sinusoidal jitter tolerance Data rate = (peak-to-peak) 3.75 Gbps Pattern = CJPAT Jitter frequency = 20 MHz Data rate = 3.75 Gbps Pattern = CJPAT December 2010 Altera Corporation (Note Typ Max Min Typ Max — 0.35 — — 0.35 > 0.37 > 0.37 > 0.65 > 0.65 > ...
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... Switching Characteristics (Part 7 of 13) C5 Typ Max Min Typ Max — — 0.2 — — — — 0.3 — — > 2 > 2 > 0.3 > 0.3 > 0.3 > 0.3 December 2010 Altera Corporation Unit ...
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... Compliance — 6.0 Gbps (G3) pattern SATA Receiver Jitter Tolerance (13) Total jitter Compliance tolerance at pattern 1.5 Gbps (G1) Deterministic Compliance jitter tolerance at pattern 1.5 Gbps (G1) December 2010 Altera Corporation (Note Typ Max Min Typ Max > 1 > 1 > 0.2 > 0.2 > 0.2 > 0.2 — 0.55 — ...
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... C5 Min Typ Max Min Typ Max 33 33 5700 5700 80 80 150 150 > 0.65 > 0.65 > 0.35 > 0. 5700 5700 75 75 150 150 > 0.60 > 0.60 > 0.18 > 0. 5700 5700 30 30 December 2010 Altera Corporation Unit kHz ppm kHz ppm kHz ppm ps ...
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... Pattern = CJPAT E.6.HV, E.12.HV Deterministic jitter tolerance Pattern = CJPAT E.6.LV, E.12.LV, E.24.LV, E.30.LV Total jitter Pattern = tolerance CJTPAT E.60.LV Pattern = PRBS31 December 2010 Altera Corporation (Note Typ Max Min Typ Max 100 100 — 0.279 — — 0.279 — 0.35 — ...
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... Switching Characteristics (Part 11 of 13) C5 Min Typ Max Min Typ Max > 0.37 > 0.37 — — > 0.55 > 0.55 — — 0.35 — — 0.35 — — 0.17 — — 0.17 > 0.37 > 0.37 > 0.55 > 0.55 December 2010 Altera Corporation Unit ...
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... MHz Pattern = CJPAT Jitter frequency = 10.9 KHz Pattern = CJPAT Sinusoidal jitter tolerance at Jitter 1536 Mbps frequency = 921.6 KHz to 20 MHz Pattern = CJPAT December 2010 Altera Corporation (Note Typ Max Min Typ Max Min > 8.5 > 8.5 > 0.1 > 0.1 > 8.5 > 8.5 > 0.1 > 0.1 Arria II Device Handbook Volume 3: Device Datasheet and Addendum 1– ...
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... Typ Max Min Typ Max > 8.5 > 8.5 > 0.1 > 0.1 inter operability point. T interpretability point. R 1), (2) (Part –C4 and –I4 Unit Min Typ Max — — 0.1 UI — — 0.01 UI — — 0.1 UI — — 0.01 UI December 2010 Altera Corporation Unit UI UI ...
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... PCIe Transmit Jitter Generation (5) Total jitter at 2.5 Gbps Compliance pattern (Gen1)—×1, ×4, and ×8 Total jitter at 5 Gbps Compliance pattern (Gen2)—×1, ×4, and ×8 December 2010 Altera Corporation (Note –C3 and –I3 Min Typ (3) 0.03 KHz > KHZ > ...
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... Min Typ Max > 0.6 Compliant 65 — 175 (6) — — 0.17 — — 0.35 Switching Characteristics 1), (2) (Part –C4 and –I4 Unit Min Typ Max — UI Compliant UI 65 — 175 UI — — 0.17 UI — — 0.35 UI December 2010 Altera Corporation ...
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... Pattern = CJPAT Data rate = 3.75 Gbps Total jitter (peak-to-peak) Pattern = CJPAT HiGig Receiver Jitter Tolerance Data rate = 3.75 Gbps Deterministic jitter tolerance (peak-to-peak) Pattern = CJPAT December 2010 Altera Corporation (Note –C3 and –I3 Min Typ (6) > 0.37 > 0.55 KHz > 8.5 MHz > ...
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... Unit Max Min Typ Max — — — — — — — — — — — — 0.3 — — 0.3 — — — — — — — — — — — — — — — December 2010 Altera Corporation ...
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... Pattern = 75% color SAS Transmit Jitter Generation (9) Total jitter at 1.5 Gbps (G1) Pattern = CJPAT Deterministic jitter at Pattern = CJPAT 1.5 Gbps (G1) Total jitter at 3.0 Gbps (G2) Pattern = CJPAT December 2010 Altera Corporation (Note –C3 and –I3 Min Typ 0.2 — 100 KHz 0.3 — ...
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... December 2010 Altera Corporation ...
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... The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification. (10) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0. (11) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1. December 2010 Altera Corporation (Note –C3 and –I3 ...
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... MHz 450 MHz Min Typ Max Unit 5 — 670 (1) MHz 5 — 622 (1) MHz 5 — 500 (1) MHz 5 — 325 MHz 600 — 1,400 MHz 40 — — — — 0.15 UI (p–p) — — ±750 ps (p–p) December 2010 Altera Corporation ...
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... PLL closed-loop medium bandwidth PLL closed-loop high bandwidth t Accuracy of PLL phase shift PLL_PSERR t Minimum pulse width on areset signal ARESET December 2010 Altera Corporation Description 100 MHz) OUT 100 MHz) OUT 100 MHz) OUT 100 MHz) OUT 100 MHz) OUT ...
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... MHz 40 — — — 700 (2) MHz — — 500 (2) MHz — — 717 (2) MHz — — 717 (2) MHz — — scanclk — 3.5 — cycles scanclk — 1 — cycles — — 100 MHz — — December 2010 Altera Corporation ...
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... Upstream PLL: 0.59 Mhz Upstream PLL BW < 1 MHz b. Downstream PLL: Downstream PLL BW > 2 MHz (7) High bandwidth PLL settings are not supported in external feedback mode. (8) External memory interface clock output jitter specifications use a different measurement method, which is available in page 1–75. December 2010 Altera Corporation Parameter Min — — — ...
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... MHz 300 250 MHz 300 250 MHz 220 180 MHz 270 220 MHz 270 220 MHz Unit –4 400 MHz 440 MHz 480 MHz 380 MHz 380 MHz 410 MHz 390 MHz 310 MHz 380 MHz December 2010 Altera Corporation ...
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... True dual port 512 × 18 single CLK True dual-port 512 × 18 single CLK, with the read-during-write option set to Old Data Min Pulse Width (clock high time) Min Pulse Width (clock low time) December 2010 Altera Corporation (Note 1) Resources Performance Used Number of – ...
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... MHz 475 475 MHz 850 850 ps 690 690 ps 380 350 MHz 385 325 MHz 205 200 MHz 255 250 MHz 330 310 MHz 205 200 MHz 435 420 MHz 400 400 MHz 860 950 ps 690 690 ps December 2010 Altera Corporation ...
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... Table 1–52 lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX and GZ devices. Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices Dev_CLRn December 2010 Altera Corporation Programming Mode Description Description Arria II Device Handbook Volume 3: Device Datasheet and Addendum ...
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... Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics C5,I5 C6 Unit Min Max Min Max 5 622 5 500 MHz 5 472.5 5 472.5 MHz 5 622 5 500 MHz 5 472.5 5 472.5 MHz 1050 150 150 840 Mbps (2) December 2010 Altera Corporation ...
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... SERDES (data rate 600 – 945 Mbps) True LVDS and emulated LVDS_E_3R with logic elements as SERDES (data rate < 600 Mbps) True LVDS and t emulated TX_DCD LVDS_E_3R December 2010 Altera Corporation I3 C4 Min Max Min Max (3) 945 (3) 945 (3) (3) (3) (3) (3) 945 ...
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... Mbps 740 640 (3) (3) Mbps (7) (7) (3) (7) (3) (7) Mbps (3) (7) (3) (7) Mbps PPM — 300 — 300 — 10,000 — 10,000 UI — 350 — 400 ps December 2010 Altera Corporation ...
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... Total jitter for data - t emulated x Jitter rate, 600 Mbps to differential I/O 1.25 Gbps standards with three external output resistor Total jitter for data network rate < 600 Mbps December 2010 Altera Corporation (Note 1), (2), (10) C3, I3 Min Typ Max 5 — 717 (3) 5 — 717 ...
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... Switching Characteristics C4, I4 Unit Typ Max — 0. — 200 ps — 300 ps — 500 ps — 100 ps — 250 ps — 1250 Mbps — (6) Mbps — (4) Mbps — (4) Mbps — 10000 UI — 300 ± PPM December 2010 Altera Corporation ...
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... One data transition is defined as a 0-to-1 or 1-to-0 transition. (3) The DPA lock time stated in the table applies to both commercial and industrial grade. (4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. December 2010 Altera Corporation (Note 1), (2), (10) (Part ...
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... Figure 1–6. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for Arria II GZ Devices at a 1.25 Gbps Data Rate Sinusoidal Jitter Amplitude (UI) 25 8.5 0.35 0.1 10,000 (F1) 17,565 (F2) Arria II Device Handbook Volume 3: Device Datasheet and Addendum 20db/dec baud/1667 1,493,000 (F3) Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Jitter Frequency (Hz) 20,000,000 Jitter Frequency (Hz) 50,000,000 (F4) December 2010 Altera Corporation ...
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... Table 1–58. DLL Frequency Range Specifications for Arria II GZ Devices (Part Frequency Range (MHz) Frequency Mode –3 0 90-130 1 120-170 2 150-210 3 180-260 4 240-320 5 290-380 6 360-450 December 2010 Altera Corporation Jitter Frequency (Hz) F1 10,000 F2 17,565 F3 1,493,000 F4 50,000,000 Specifications. Resolution I3, C5 90-130 90-110 110-170 110-150 ...
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... DQS Delay Number of Buffer Mode Delay (1) Chains High 6 (Note 1), (2), (3) Max Unit 13.0 ps 15 for Arria II GZ DQS_PSERR –4 Unit 120 ps (Note 1), (2), (3) (Part –5 –6 Unit Max Min Max 125 -125 125 ps 250 -250 250 ps December 2010 Altera Corporation ...
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... The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible. (3) The memory output clock jitter stated in Duty Cycle Distortion (DCD) Specifications Table 1– ...
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... Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics (Note 1) C4, I4 Unit Min Max Slow Model Unit 0.713 0.796 0.801 0.873 0.585 0.654 0.661 0.722 2.520 2.733 2.775 2.944 2.503 2.732 2.774 2.944 0.124 0.147 0.147 0.167 December 2010 Altera Corporation ...
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... You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column. (2) Minimum offset does not include the intrinsic delay. I/O Timing Altera offers two ways to determine I/O timing: Using the Microsoft Excel-based I/O Timing. ■ ...
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... High-speed I/O block: Maximum/minimum LVDS data transfer rate f HSDRDPA (f = 1/TUI), DPA. HSDRDPA Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter 1: Device Datasheet for Arria II Devices Definitions Glossary Positive Channel ( Negative Channel ( Ground p − Positive Channel ( Negative Channel ( Ground p − December 2010 Altera Corporation ...
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... Diagram of PLL Specifications ( PLL Core Clock Specifications Note: (1) CoreClock can only be fed by dedicated clock input pins or PLL outputs Receiver differential input discrete resistor (external to the Arria II device December 2010 Altera Corporation Definitions t JCP JCH JCL JPSU t t JPZX JPCO Switchover CLK f ...
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... Signal low-to-high transition time (20-80%). RISE Arria II Device Handbook Volume 3: Device Datasheet and Addendum Definitions Bit Time Sampling Window RSKM 0.5 x TCCS (SW REF V OL Chapter 1: Device Datasheet for Arria II Devices Glossary RSKM 0.5 x TCCS V CCIO IH(DC) V IL(DC) V IL( variation and CO /w) C December 2010 Altera Corporation ...
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... OCM Output differential voltage swing: The difference in voltage between the positive and V OD complementary conductors of a differential transmission at the transmitter High-speed I/O block: The clock boost factor December 2010 Altera Corporation Definitions Arria II Device Handbook Volume 3: Device Datasheet and Addendum 1–81 ...
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... Table 1–5, Table 1–37, Table 1–40, Table 1–42, Table 1–44, 1–63. Figure 1–5. Chapter 1: Device Datasheet for Arria II Devices Document Revision History 1–6, Table 1–7, Table 1–11, Table 1–35, Table 1–45, Table 1–57, Table 1–61, and December 2010 Altera Corporation ...
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... Table 1–26, Table 1–29, Table 1–30, Table 1–31, Table 1–32, and Table 1–33. June 2009 1.2 Added Table 1–32. ■ Updated Equation 1–1. ■ March 2009 1.1 Added “I/O Timing” section. February 2009 1.0 Initial release. December 2010 Altera Corporation Changes Arria II Device Handbook Volume 3: Device Datasheet and Addendum 1–83 ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter 1: Device Datasheet for Arria II Devices Document Revision History December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter 2: Addendum for the Arria II Device Handbook Document Revision History December 2010 Altera Corporation ...
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... Technical training Product literature Non-technical support (General) (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital ...
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... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Additional Information Typographic Conventions page of the Altera December 2010 Altera Corporation ...