EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 316

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–36
Table 9–14. Dedicated Configuration Pin Connections During JTAG Configuration (Part 2 of 2)
Figure 9–17. JTAG Configuration of Multiple Devices Using a Download Cable
Notes to
(1) Connect the pull-up resistors to the V
(2) You must connect the pull-up resistor to the same supply voltage, V
(3) Resistor value can vary from 1 K
(4) In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables, pin 6 is a no connect.
(5) You must connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use JTAG configuration, connect nCONFIG
(6) You must connect nCE to GND or drive it low for successful JTAG configuration.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
nSTATUS
CONF_DONE
DCLK
Pin 1
devices.
ByteBlaster II, ByteBlasterMV, EthernetBlaster, EthernetBlaster II, or MasterBlaster cable.
to the V
board.
10-Pin Male Header
Signal
Download Cable
(JTAG Mode)
Figure
V
CCIO
V
CCPD
CCIO
for Arria II GX device, V
(2)
9–17:
/
V
(4)
V
IO
1 kΩ
V
CCPD
(3)
Pull to V
each nSTATUS pin must be pulled up to V
Pull to V
chain, each CONF_DONE pin must be pulled up to V
the end of JTAG configuration indicates successful configuration.
Do not leave DCLK floating. Drive low or high, whichever is more convenient on your board.
V
CCIO
CCIO
(2)
/
(2)
/V
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board
buffer.
JTAG-chain device programming is ideal when the system contains multiple devices
or when testing your system using JTAG BST circuitry.
Figure 9–17
CCPD
(3)
CCIO
CCIO
or V
V
or V
Ω
CCIO
(5)
(5)
(5)
to 10 K
CCPGM
/V
(1)
CCIO
CCPGM
CCPGM
CCPGM
10 kΩ
TDI
nSTATUS
nCONFIG
DCLK
MSEL[n..0]
nCE
shows a multi-device JTAG configuration when using a download cable.
power supply of I/O bank 3C for Arria II GX devices and to V
for Arria II GZ device, and MSEL to GND. Pull DCLK either high or low, whichever is convenient on your
TMS
Ω
Arria II Device
(6)
using a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain,
.
using a 10-
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
CONF_DONE
TCK
V
TDO
CCIO
kΩ resistor. When configuring multiple devices in the same JTAG
/V
(1)
CCPGM
10 kΩ
CCIO
V
(5)
(5)
(5)
CCIO
CCIO
/V
(1)
for Arria II GX devices or V
or V
CCPGM
Description
10 kΩ
TDI
nSTATUS
nCONFIG
DCLK
MSEL[n..0]
nCE
TMS
CCPGM
CCIO
Arria II Device
(6)
CONF_DONE
or V
TCK
individually.
CCPGM
V
TDO
CCIO
/V
(1)
individually. CONF_DONE going high at
CCPGM
CCPD
10 kΩ
CCPGM
V
(5)
(5)
(5)
CCIO
for Arria II GZ devices as the USB-Blaster,
/V
(1)
at a 3.0-V power supply for Arria II GZ
CCPGM
10 kΩ
TDI
nSTATUS
nCONFIG
DCLK
MSEL[n..0]
nCE
December 2010 Altera Corporation
Stratix II or Stratix II GX
TMS
(6)
Arria II Device
Device
CONF_DONE
TCK
TDO
JTAG Configuration
V
CCIO
/V
(1)
CCPGM
10 kΩ