EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 407

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
Receiver Channel Datapath
Figure 1–23. Receiver Channel Datapath
December 2010 Altera Corporation
Receiver PMA
f
f
■
■
For more information about the available settings in each feature, refer to the
Datasheet for Arria II Devices.
Figure 1–22
Figure 1–22. Transmitter Output Buffer
This section describes the Arria II GX and GZ receiver channel datapath architecture.
The sub-blocks in the receiver datapath are described in order from the receiver input
buffer to the RX phase compensation FIFO buffer at the FPGA fabric-to-transceiver
interface.
Figure 1–23
This section describes the receiver PMA modules, which consists of the receiver input
buffer, CDR, and deserializer.
The rx_analogreset signal resets all modules in the receiver PMA block. For more
information about this signal, refer to the
Devices
Receiver-detect capability to support PCIe functional mode—This circuit detects if
there is a receiver downstream by sending out a pulse on the common mode of the
transmitter and monitoring the reflection. For more information, refer to
Mode” on page
Tristate-able transmitter buffer to support PCIe electrical idle—This feature is only
active in PCIe mode to work hand-in-hand with the receiver-detect capability. For
more information, refer to
chapter.
shows the transmitter output buffer block diagram.
shows the receiver channel datapath in Arria II GX and GZ devices.
Programmable
Pre-Emphasis
and V
OD
1–62.
Receiver Channel PCS
“PCIe Mode” on page
Receiver
Detect
Reset Control and Power Down in Arria II
+ VTT -
Arria II Device Handbook Volume 2: Transceivers
50 W
50 W
1–62.
Transmitter
Receiver Channel
Output
Pins
Input Reference
PMA
Clock
“PCIe
Device
Serial Input
Data
rx_datain
1–21