EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 403

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Transmitter Channel Datapath
December 2010 Altera Corporation
Table 1–5
on the data.
Table 1–5. tx_forcedisp and tx_dispval Port Values for Arria II Devices
Figure 1–18
is shown in hexadecimal radix.
Figure 1–18. 8B/10B Encoder Force Running Disparity Operations
In this example, a series of K28.5 code groups are continuously sent. The stream
alternates between a positive running disparity K28.5 (RD+) and a negative running
disparity K28.5 (RD-) to maintain a neutral overall disparity. The current running
disparity at time n + 3 indicates that the K28.5 in time n + 4 must be encoded with a
negative disparity. Because tx_forcedisp is high at time n + 4, and tx_dispval is also
high, the K28.5 at time n + 4 is encoded as a positive disparity code group.
The optional tx_invpolarity port is available in all functional modes to dynamically
enable the transmitter polarity inversion feature as a workaround to board re-spin or
a major update to the FPGA fabric design when the positive and negative signals of a
serial differential link are accidentally swapped during board layout.
A high value on the tx_invpolarity port inverts the polarity of every bit of the input
data word to the serializer in the transmitter datapath. Correct data is seen by the
receiver, because inverting the polarity of each bit has the same effect as swapping the
positive and negative signals of the differential link. The tx_invpolarity signal is
dynamic and might cause initial disparity errors at the receiver of an 8B/10B encoded
link. The downstream system must be able to tolerate these disparity errors.
tx_forcedisp
Current Running Disparity
0
1
1
lists the tx_forcedisp and tx_dispval port values and the effects they have
shows an example of tx_forcedisp and tx_dispval port use, where data
tx_ctrlenable
tx_forcedisp
dataout[9:0]
tx_dispval
tx_dispval
tx_in[7:0]
X
0
1
clock
n
RD-
17C
BC
Current running disparity has no change.
Encoded data has negative disparity.
Encoded data has positive disparity.
n + 1
RD+
283
BC
n + 2
17C
RD-
BC
n + 3
RD+
283
BC
n + 4
Arria II Device Handbook Volume 2: Transceivers
Description
RD+
283
BC
n + 5
RD-
17C
BC
n + 6
RD+
283
BC
n + 7
17C
RD-
BC
1–17