EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 112

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–8
Figure 5–6. Device Dual-Regional Clock Region for Arria II GX Devices
Figure 5–7. Device Dual-Regional Clock Region for Arria II GZ Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Clock Network Sources
PLL_4
L2
L3
PLL_1
Figure 5–6
In Arria II GX devices, clock input pins, internal logic, transceiver clocks, and PLL
outputs can drive the GCLK and RCLK networks, while in Arria II GZ devices, clock
input pins, PLL outputs, and internal logic can drive the GCLK and RCLK networks.
Table 5–2
clock pins and the GCLK and RCLK networks.
T1 T2
B1 B2
through
and
R2
R3
PLL_2
PLL_3
Figure 5–7
Table 5–5 on page 5–10
show the dual-regional clock region for Arria II devices.
Regional clock
multiplexer
Regional clock
multiplexers
list the connectivity between dedicated
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock pins or PLL outputs
can drive half of the device to
create side-wide clocking
regions for improved
interface timing.
Clock pins or PLL outputs
can drive half of the device to
create side-wide clocking
regions for improved
interface timing.
December 2010 Altera Corporation
Clock Networks in Arria II Devices