EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 22

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–8
Table 1–5. Sample of Supported Protocols and Feature Descriptions for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
PCIe
XAUI/HiGig/HiGig+
Gbe
CPRI/OBSAI
Supported Protocols
1
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Table 1–5
implementing these protocols.
For other protocols supported by Arria II devices, such as SONET/SDH, SDI, SATA
and SRIO, refer to the
Diagnostic features
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Serial loopback from the transmitter serializer to the receiver CDR for
transceiver physical coding sublayer (PCS) and PMA diagnostics
Parallel loopback from the transmitter PCS to the receiver PCS with built-in self
test (BIST) pattern generator and verifier
Reverse serial loopback pre- and post-CDR to transmitter buffer for physical
link diagnostics
Loopback master and slave capability in PCIe hard IP blocks
Support for protocol features such as MSB-to-LSB transmission in a
SONET/SDH configuration and spread-spectrum clocking in a PCIe
configuration
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lists common protocols and the Arria II dedicated circuitry and features for
Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCIe Base
Specification 2.0 that includes PHY/MAC, Data Link, and Transaction layer circuitry
embedded in the PCIe hard IP blocks.
PCIe Gen1 has ×1, ×2, ×4, and ×8 lane configurations. PCIe Gen2 has ×1, ×2, and ×4
lane configurations. PCIe Gen2 does not support ×8 lane configurations
Built-in circuitry for electrical idle generation and detection, receiver detect, power state
transitions, lane reversal, and polarity inversion
8B/10B encoder and decoder, receiver synchronization state machine, and ±300 PPM
clock compensation circuitry
Options to use:
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Compliant to IEEE P802.3ae specification
Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from
idle ordered sets (||A||, ||K||, ||R||) at the transmitter and receiver, respectively
8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and
±100 PPM clock compensation circuitry
Compliant to IEEE 802.3 specification
Automatic idle ordered set (/I1/, /I2/) generation at the transmitter, depending on the
current running disparity
8B/10B encoder and decoder, receiver synchronization state machine, and ±100 PPM
clock compensation circuitry
Transmit bit slipper eliminates latency uncertainty to comply with CPRI/OBSAI
specifications
Optimized for power and cost for remote radio heads and RF modules
Hard IP Data Link Layer and Transaction Layer
Hard IP Data Link Layer and custom Soft IP Transaction Layer
Transceiver Architecture in Arria II Devices
Feature Descriptions
Chapter 1: Overview for the Arria II Device Family
December 2010 Altera Corporation
chapter.
Arria II Device Architecture