EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 488

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–102
Table 1–35. ALTGX Megafunction PIPE Interface Ports for Arria II Devices (Available only in PCIe functional mode)
Table 1–36. ALTGX Megafunction Reset and Power Down Ports for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
tx_forceelecidle
pipeelecidle
pipephydonestatus
pipestatus
rx_pipedatavalid
gxb_powerdown
rx_analogreset
rx_digitalreset
tx_digitalreset
(Part 2 of 2)
Port Name
Port Name
f
Table 1–36
megafunction.
For more information, refer to the
chapter.
Input/Output
Input/Output
Input
Input
Input
Input
Output
Output
Output
Output
Input
lists the reset and power down port names and descriptions for the ALTGX
Asynchronous transceiver block power down signal. When asserted high, all
digital and analog circuitry in the PCS, PMA, CMU of the transceiver block is
powered down, except for the refclk buffers.
Active-high receiver PMA reset.
Active-high receiver PCS reset.
Active-high transmitter PCS reset.
Force transmitter buffer to PCIe electrical idle signal levels. Functionally
equivalent to the TxElecIdle signal defined in PIPE specification revision
2.00.
Asynchronous signal to indicate whether electrical idle is detected or inferred at
the receiver. Functionally equivalent to the RxElecIdle signal defined in PIPE
specification revision 2.00.
If you enable the electrical idle inference block, it drives this signal high when it
infers an electrical idle condition, as described in
page
block is disabled, the rx_signaldetect signal from the signal detect circuitry
in the receiver input buffer is inverted and driven on this port.
PHY function completion indicator. Functionally equivalent to the PhyStatus
signal defined in PIPE specification revision 2.00. Asserted high for one parallel
clock cycle to communicate completion of several PHY functions, such as
power state transition and receiver detection.
PCIe receiver status port. Functionally equivalent to the RxStatus[2:0] signal
defined in PIPE specification revision 2.00. The width of this signal is 3 bits per
channel. The encoding of receiver status on the pipestatus port is as follows:
■
■
■
■
■
■
■
■
Valid data and control on the rx_dataout and rx_ctrldetect ports
indicator. Functionally equivalent to the RxValid signal defined in PIPE
specification revision 2.00.
000—Received data OK
001—1 skip added
010—1 skip removed
011—Receiver detected
100—8B/10B decoder error
101—Elastic buffer overflow
110—Elastic buffer underflow
111—Received disparity error
1–70. Otherwise, it drives this signal low. If the electrical idle inference
Reset Control and Power Down in Arria II Devices
Chapter 1: Transceiver Architecture in Arria II Devices
Description
Description
December 2010 Altera Corporation
“Electrical Idle Inference” on
Transceiver Port List