EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 582

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–8
Figure 4–4. Sample Reset Sequence for Four Receiver and Transmitter Channels—Receiver CDR in Automatic Lock
Mode
Arria II Device Handbook Volume 2: Transceivers
Reset Signals
Output Status Signals
rx_freqlocked[0]
rx_freqlocked[3]
pll_powerdown
rx_analogreset
rx_digitalreset
tx_digitalreset
pll_locked
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and receiver channel. For XAUI
functional mode, with the receiver CDR in automatic lock mode, use the reset
sequence shown in
As shown in
CDR in automatic lock mode configuration:
1. After power up, assert pll_powerdown for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high,
4. For the receiver operation, after de-assertion of the busy signal, wait for two
busy
between markers 1 and 2).
asserted during this time period. After you de-assert the pll_powerdown signal,
the transmitter PLL starts locking to the transmitter input reference clock.
de-assert the tx_digitalreset signal. At this point, the transmitter is ready for
data traffic.
parallel clock cycles to de-assert the rx_analogreset signal. After rx_analogreset
is de-asserted, the receiver CDR of each channel starts locking to the receiver input
reference clock.
1
1 μs
Figure
2
3
Figure
4–4, perform the following reset sequence steps for the receiver
4
Two parallel clock cycles
5
4–4.
6
Chapter 4: Reset Control and Power Down in Arria II Devices
7
7
4 μs
8
December 2010 Altera Corporation
Transceiver Reset Sequences