EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 414

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–28
Arria II Device Handbook Volume 2: Transceivers
1
Automatic Lock Mode
In automatic lock mode, the LTR/LTD controller relies on the PPM detector and the
phase relationship detector to set the CDR in LTR or LTD mode. Initially, the CDR is
set to LTR mode. After the CDR locks to the input reference clock, the LTR/LTD
controller automatically sets it to LTD mode and asserts the rx_freqlocked signal
when the following three conditions are met:
■
■
■
If the CDR does not stay locked-to-data due to frequency drift or severe amplitude
attenuation, the LTR/LTD controller switches the CDR back to LTR mode to lock to
the input reference clock. The LTR/LTD controller switches the CDR from LTD to LTR
mode and de-asserts the rx_freqlocked signal when the following conditions are met:
■
■
Manual Lock Mode
You may want to use manual lock mode if your application requires faster CDR lock
time. In manual lock mode, the LTR/LTD controller sets the CDR in LTR or LTD
mode, depending on the logic level on the rx_locktorefclk and rx_locktodata
signals, as shown in
When the rx_locktorefclk signal is asserted high, the rx_freqlocked signal does not
have significance and is always driven low, indicating that the CDR is in LTR mode.
When the rx_locktodata signal is asserted high, the rx_freqlocked signal is always
driven high, indicating that the CDR is in LTD mode. If both signals are de-asserted,
the CDR is in automatic lock mode.
You must comply with the different transceiver reset sequences depending on the
CDR lock mode.
Signal threshold detection circuitry indicates the presence of valid signal levels at
the receiver input buffer
CDR output clock is within the configured PPM frequency threshold setting with
respect to the input reference clock (frequency is locked)
CDR output clock and input reference clock are phase matched within
approximately 0.08 UI (phase is locked)
Signal threshold detection circuitry indicates the absence of valid signal levels at
the receiver input buffer
CDR output clock is not in the configured PPM frequency threshold setting with
respect to the input reference clock
Table 1–8 on page
1–27.
Chapter 1: Transceiver Architecture in Arria II Devices
December 2010 Altera Corporation
Receiver Channel Datapath