EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 426

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Table 1–13. Synchronization State Machine Parameters for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Number of valid synchronization code groups or ordered sets
received to achieve synchronization
Number of erroneous code groups received to lose
synchronization
Number of continuous good code groups received to reduce
the error count by one
Automatic Synchronization State Machine Mode
You must use this mode with 8B/10B encoded data if the input data to the word
aligner is 10 bits.
Protocols such as PCIe, XAUI, Gigabit Ethernet, and Serial RapidIO require the
receiver PCS logic to implement a synchronization state machine to provide hysteresis
during link synchronization. Each of these protocols defines a specific number of
synchronization code groups that the link must receive to acquire synchronization
and a specific number of erroneous code groups that it must receive to fall out of
synchronization.
The Quartus II software configures the word aligner in automatic synchronization
state machine mode for PCIe, XAUI, Gigabit Ethernet, and Serial RapidIO functional
modes. It automatically selects the word alignment pattern length and the word
alignment pattern as specified by each protocol. In each of these functional modes, the
protocol-compliant synchronization state machine is implemented in the word
aligner.
By using Basic functional mode with the 10-bit PMA-PCS interface, you can configure
the word aligner in automatic synchronization state machine mode by selecting the
Use the automatic synchronization state machine option in the ALTGX MegaWizard
Plug-In Manager. Basic mode also allows you to program a custom 7-bit or 10-bit
word alignment pattern that the word aligner uses for synchronization.
Table 1–13
software allows in supported functional modes. The synchronization state machine
parameters are fixed for PCIe, XAUI, GIGE, and Serial RapidIO modes as specified by
the respective protocol. You can program these parameters as suited to your
proprietary protocol implementation for Basic mode.
After de-assertion of the rx_digitalreset signal in automatic synchronization state
machine mode, the word aligner starts looking for the word alignment pattern or
synchronization code groups in the received data stream. When the programmed
number of valid synchronization code groups or ordered sets is received, the
rx_syncstatus signal is driven high to indicate that synchronization is acquired. The
rx_syncstatus signal is constantly driven high until the programmed number of
erroneous code groups is received without receiving intermediate good groups; after
which the rx_syncstatus signal is driven low. The word aligner indicates loss of
synchronization (rx_syncstatus signal remains low) until the programmed number
of valid synchronization code groups are received again.
Parameter
lists the synchronization state machine parameters that the Quartus II
PCIe
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16
4
Chapter 1: Transceiver Architecture in Arria II Devices
XAUI
4
4
4
GIGE
3
4
4
December 2010 Altera Corporation
RapidIO
Serial
Receiver Channel Datapath
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255
3
1–256
1–256
Basic
Mode
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