EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 484

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–98
Table 1–28. ALTGX Megafunction Byte Ordering Block Ports for Arria II GX and GZ Devices
Table 1–29. ALTGX Megafunction RX Phase Compensation FIFO Ports for Arria II Devices
Table 1–30. ALTGX Megafunction Receiver PMA Ports for Arria II Devices (Part 1 of 2)
Arria II Device Handbook Volume 2: Transceivers
rx_enabyteord
rx_byteorderalignstatus
coreclkout
rx_coreclk
rx_clkout
tx_clkout
rx_dataout
rx_phase_comp_
fifo_error
rx_cruclk
rx_datain
rx_locktodata
Port Name
Port Name
Port Name
Table 1–28
megafunction.
Table 1–29
ALTGX megafunction.
Table 1–30
descriptions for the ALTGX megafunction.
Input/Output
Input/Output
Input/Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
lists the byte ordering block port names and descriptions for the ALTGX
lists the RX phase compensation FIFO port names and descriptions for the
lists the receiver physical medium attachment (PMA) port names and
Clock from the CMU0 block of the associated transceiver block or the master
transceiver block for ×4 bonded or ×8 bonded channel configurations,
respectively. This is the default read and write clocks for those configurations.
Optional read clock port for the RX phase compensation FIFO. If not enabled,
the Quartus II software automatically selects
rx_clkout/tx_clkout/coreclkout as the read clock for the RX phase
compensation FIFO. If selected, you must drive this port with a clock that has 0
PPM difference with respect to the FIFO write clock.
Recovered clock from the receiver channel. This is the default read and write
clocks for the RX phase compensation FIFO in non-bonded configurations
without the rate-match FIFO.
Clock from the transmitter channel local clock divider. This is the default read
and write clocks for the RX phase compensation FIFO in non-bonded
configurations with the rate-match FIFO.
Parallel data output from the receiver to the FPGA fabric. The bus width
depends on the channel width multiplied by the number of channels per
instance.
RX phase compensation FIFO full or empty indicator. A high level indicates that
the RX phase compensation FIFO is either full or empty.
Asynchronous enable byte ordering control. The byte ordering block is
rising-edge sensitive to this signal. A low-to-high transition triggers the byte
ordering block to restart the byte ordering operation.
Byte ordering status indicator. A high level indicates that the byte ordering
block has detected the programmed byte ordering pattern in the LSByte of the
received data from the byte deserializer.
Input reference clock for the receiver CDR.
Receiver serial data input port.
Asynchronous receiver CDR LTD mode control signal. When asserted high, the
receiver CDR is forced to LTD mode. When de-asserted low, the receiver CDR
lock mode depends on the rx_locktorefclk signal level.
Chapter 1: Transceiver Architecture in Arria II Devices
Description
Description
Description
December 2010 Altera Corporation
Transceiver Port List