EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 480

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–94
Transceiver Port List
Table 1–23. ALTGX Megafunction CMU Ports for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
pll_inclk
pll_powerdown
coreclkout
pll_locked
Port Name
1
■
You instantiate the Arria II GX and GZ transceivers with the ALTGX megafunction
instance in the Quartus II MegaWizard Plug-In Manager. The ALTGX megafunction
instance allows you to configure the transceivers for your intended protocol and
select optional control and status ports to and from the instantiated transceiver
channels.
These signals are available if you enable the block associated with them.
Table 1–23
Input/Output
Transceiver channel reconfiguration—for transceiver channels, dynamic
reconfiguration involves the reconfiguration of the following:
■
1
■
■
1
Output
Output
Input
Input
Data Rate Reconfiguration—achievable by switching between two TX PLLs set
to different data rates or reconfiguring the RX PLLS or reconfiguring the local
dividers in the transmit side
CMU PLL Reconfiguration
Functional Mode Reconfiguration
Ensure that the functional mode of the transceiver channel supports the
reconfigured data rate.
Ensure that the various clocks involved support the transition.
lists the CMU port names and descriptions for the ALTGX megafunction.
Input reference clock for the CMU PLL.
Asynchronous active-high signal to power down both CMU PLLs. The minimum
pulse width for this signal is specified in the
chapter.
Note: Asserting the pll_powerdown signal does not power down the refclk
buffers.
Note: While each CMU PLL has its own pll_powerdown port, the ALTGX
MegaWizard Plug-In Manager instantiation provides only one port per transceiver
block. This port power downs one or both CMU PLLs (if used).
A low-speed parallel clock generated by the CMU0 clock divider for bonded
channel configurations. This signal is generated by the CMU0 clock divider in the
master transceiver block in ×8 bonded channel configurations and is not available
in non-bonded channel configurations.
If the byte serializer block is enabled in bonded channel modes, the coreclkout
clock output is half the frequency of the low-speed parallel clock. Otherwise, the
coreclkout clock output is the same frequency as the low-speed parallel clock.
You can also use this clock on the write and read clock ports of the TX phase
compensation FIFOs in all bonded channels if tx_coreclk is not enabled in the
ALTGX MegaWizard Plug-In Manager.
Asynchronous active-high signal to indicate whether the CMU PLL is locked.
Chapter 1: Transceiver Architecture in Arria II Devices
Description
Device Datasheet for Arria II Devices
December 2010 Altera Corporation
Transceiver Port List