EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 517

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–17. Receiver Datapath Clocking in ×8 Bonded Channel Configuration
December 2010 Altera Corporation
Fabric
FPGA
hard IP
hard IP
PCIe
PCIe
coreclkout
Figure 2–17
The CDR in each of the eight receiver channels recovers the serial clock from the
received data on that channel. The serial recovered clock frequency is half the
configured data rate. The serial recovered clock is divided within each channel’s
receiver PMA to generate the parallel recovered clock. The deserializer uses the serial
recovered clock in the receiver PMA. The parallel recovered clock and deserialized
data from the receiver PMA in each channel is forwarded to the receiver PCS in that
channel.
Slave Transceiver Block
Interface
Interface
Master Transceiver Block
PIPE
PIPE
shows receiver datapath clocking in ×8 bonded channel configuration.
Input Reference Clock
Input Reference Clock
/2
/2
/2
CMU1_PLL
CMU0_PLL
CMU1_PLL
CMU0_PLL
Receiver Channel PCS
Receiver Channel PCS
CMU1 Clock Divider
CMU0 Clock Divider
CMU1 Clock Divider
CMU0 Clock Divider
Arria II Device Handbook Volume 2: Transceivers
CMU1_Channel
CMU0_Channel
CMU1_Channel
CMU0_Channel
Low-Speed Parallel Clock from CMU0 Clock Divider
FPGA Fabric-Transceiver Interface Clock
Parallel Recovered Clock
Serial Recovered Clock
Receiver Channel
Receiver Channel
PMA
PMA
Reference
Reference
Clock
Clock
Input
Input
2–27