EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 479

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Dynamic Reconfiguration
December 2010 Altera Corporation
The dynamic reconfiguration controller requires input from one of the following:
■
■
The different modes of dynamic reconfiguration are:
■
■
Its input ports through user logic where they are translated to the address and
data bus inside the controller. The address and data bus are then converted into
serial data and forwarded to the selected transceiver channel
A Memory Initialization File (.mif) where the controller receives 16-bit words from
the .mif that you generate and sends this information to the transceiver channel
selected
PMA settings reconfiguration, available for the following PMA settings:
■
■
■
■
Receiver offset cancellation
1
f
f
Process variations create offsets in analog circuit voltages, pushing them outside
the expected range. The Arria II GX and GZ devices provide an offset cancellation
circuit per receiver channel to counter the offset variations due to process.
Calibration of the offset cancellation circuit is done at power-up. The receiver
input buffer and receiver CDR require offset calibration. Offset cancellation is
automatically executed whenever the device is powered on. The control logic for
offset cancellation is integrated into the dynamic reconfiguration controller.
The offset cancellation for the receiver channels option is automatically enabled in
both the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers for
Receiver, Transmitter, and Receiver only configurations. It is not available for
Transmitter only configurations.
You must always connect the ALTGX_RECONFIG instance to the ALTGX (with
receiver channels) instance in your design. Connect the reconfig_fromgxb,
reconfig_togxb, and necessary clock signals to both the ALTGX_RECONFIG and
ALTGX (with receiver channels) instances.
Pre-emphasis settings
Equalization settings
DC gain settings
V
OD
When offset cancellation is automatically enabled, you must instantiate the
dynamic reconfiguration controller to connect the reconfiguration ports
created by the ALTGX MegaWizard Plug-In Manager.
For more information about implementing the ALTGX_RECONFIG
MegaWizard Plug-In Manager, refer to
Reconfiguration in Arria II
The offset cancellation process changes the transceiver reset sequence. For
more information, refer to the
settings
Devices.
Reset Control and Power Down
AN 558: Implementing Dynamic
Arria II Device Handbook Volume 2: Transceivers
chapter.
1–93