EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 131

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–20. Phase Relationship Between Clock and Data in Source-Synchronous Mode in Arria II Devices
December 2010 Altera Corporation
Source-Synchronous Mode
If data and clock arrive at the same time on the input pins, the same phase
relationship is maintained at the clock and data ports of any IOE input register.
Figure 5–20
mode. This mode is recommended for source-synchronous data transfers. Data and
clock signals at the IOE experience similar buffer delays as long as you use the same
I/O standard.
Source-synchronous mode compensates for the delay of the clock network used plus
any difference in the delay between these two paths:
■
■
You can use the PLL Compensation assignment in the Quartus II software
Assignment Editor to select which input pins are used as the PLL compensation
targets. You can include your entire data bus, provided the input registers are clocked
by the same output of a source-synchronous compensated PLL. All input pins must
be on the same side of the device for the clock delay to be properly compensated. The
PLL compensates for the input pin with the longest pad-to-register delay among all
input pins in the compensated bus.
If you do not assign the PLL Compensation assignment, the Quartus II software
automatically selects all pins driven by the compensated output of the PLL as the
compensation target.
Data pin-to-IOE register input
Clock input pin-to-the PLL PFD input
Clock at register
reference clock
Data at register
at input pin
shows an example waveform of the clock and data in source-synchronous
Data pin
PLL
Arria II Device Handbook Volume 1: Device Interfaces and Integration
5–27