EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 405
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
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Manufacturer:
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Quantity:
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Chapter 1: Transceiver Architecture in Arria II Devices
Transmitter Channel Datapath
Figure 1–21. Serializer Bit Order
Note to
(1) The input data to the serializer is 8 bits (channel width = 8 bits with the 8B/10B encoder disabled).
December 2010 Altera Corporation
Low-Speed Parallel Clock
High-Speed Serial Clock
Figure
tx_datain[7:0]
tx_dataout[0]
1–21:
Serializer
The serializer converts the incoming low-speed parallel signal from the transceiver
PCS to the high-speed serial data and sends its LSB first to the transmitter output
buffer.
interface.
Figure 1–20. Serializer Block in an 8-Bit PCS-PMA Interface
Note to
(1) This clock is provided by the CMU0 clock divider of the master transceiver block and is only used in ×8 mode.
Figure 1–21
Parallel Clock from Master Transceiver Block (1)
00000000
Serial Clock from Master Transceiver Block (1)
Parallel Clock from CMU0 Clock Divider
Figure
Parallel Clock from Local Divider Block
Figure 1–20
Serial Clock from CMU0 Clock Divider
Serial Clock from Local Divider Block
(Note 1)
1–20:
shows an example of serialized data with a 8'b01101010 value.
Data from the PCS Block
shows the serializer block diagram in an 8-bit PCS-to-PMA
01101010
0
1
0
1
0
1
8
1
Parallel Clock
0
Low-Speed
High-Speed
Serial Clock
Arria II Device Handbook Volume 2: Transceivers
D7
D6
D5
D4
D3
D2
D1
D0
00000000
D7
D6
D5
D4
D3
D2
D1
D0
To Output Buffer
1–19
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