EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 505

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
Figure 2–8
Figure 2–8. One PCIe ×8 Link in Two Transceiver Block Arria II GX Devices
Figure 2–9
devices.
Figure 2–9. One PCIe ×8 Link in Three Transceiver Block Arria II GX Devices
Note to
(1) Arria II GX and GZ devices with three transceiver blocks allow a maximum of one PCIe ×8 link occupying two
transceiver blocks. You can configure the other transceiver block to implement other functional modes.
Figure
shows the PCIe ×8 link in two transceiver block Arria II GX devices.
shows the PCIe ×8 link in three transceiver block devices for Arria II GX
2–9:
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
Transceiver Block
Transceiver Block
EP2AGX95EF29, EP2AGX125EF29, EP2AGX190EF29,
EP2AGX260EF29, EP2AGX95EF35, EP2AGX125EF35
Transceiver Block
GXBL1 (Slave)
GXBL0(Master)
Transceiver Block GXBL1
Transceiver Block GXBL0
EP2AGX45DF25, EP2AGX65DF25, EP2AGX95DF25,
EP2AGX125DF25, EP2AGX45DF29,EP2AGX65DF29
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBL2
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
(Master)
(Slave)
First PCIe x8 Link
Arria II Device Handbook Volume 2: Transceivers
(Note 1)
2–15