EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 358

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–8
Arria II Device Handbook Volume 1: Device Interfaces and Integration
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (refer to
where n is between 1 and 8. The divisor ranges from 2 through 256 (refer to
Equation
Equation 10–1.
The EMR is updated whenever an error occurs. If the error location and message are
not shifted out before the next error location is found, the previous error location and
message are overwritten by the new information. To avoid this, you must shift these
bits out within one frame CRC verification. The minimum interval time between each
update for the EMR depends on the device and the error detection clock frequency.
However, slowing down the error detection clock frequency slows down the error
recovery time for the SEU event.
Table 10–7
EMR in Arria II devices.
Table 10–7. Minimum Update Interval for Error Message Register in Arria II Devices
The CRC calculation time for the error detection circuitry to check from the first until
the last frame depends on the device and the error detection clock frequency.
1
10–1).
The error detection frequency reflects the frequency of the error detection
process for a frame because the CRC calculation in Arria II devices is done
on a per-frame basis.
lists the estimated minimum interval time between each update for the
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ225
EP2AGZ300
EP2AGZ350
EP2AGX45
EP2AGX65
EP2AGX95
“Software Support” on page
Device
error detection frequency
10–9). The divisor is a power of two (2),
=
Chapter 10: SEU Mitigation in Arria II Devices
100MHz
---------------------- -
2
n
Timing Interval (μs)
December 2010 Altera Corporation
11.04
11.04
14.88
14.88
19.64
19.64
19.8
21.8
21.8
Error Detection Timing