EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 300

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–20
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1
The serial clock (DCLK) generated by the Arria II device controls the entire
configuration cycle and provides timing for the serial interface. During the
configuration, Arria II devices use an internal oscillator or an external clock source to
generate DCLK. At the initial stage of the configuration cycle, the Arria II device
generates a default DCLK (40 MHz maximum) from the internal oscillator to read the
header information of the programming data stored in the EPCS. After the header
information is read from the EPCS, depending on the clock source being selected, the
configuration cycle continues with a slow clock (20 MHz maximum) or a fast clock
(40 MHz maximum) from the internal oscillator or an external clock from CLKUSR
(40 MHz maximum). You can change the clock source option in the Quartus II
software from the Configuration tab of the Device and Pin Options dialog box.
Arria II GZ devices only support fast AS configuration (40 MHz maximum) and do
not support a slow clock.
In AS and fast AS configuration schemes, Arria II devices drive out control signals on
the falling edge of DCLK. The serial configuration device responds to the instructions
by driving out configuration data on the falling edge of DCLK. Then the data is latched
into the Arria II device on the following falling edge of DCLK.
In configuration mode, Arria II devices enable the serial configuration device by
driving the nCSO output pin low, which connects to the chip select (nCS) pin of the
configuration device. The Arria II device uses the serial clock (DCLK) and serial data
output (ASDO) pins to send operation commands, read address signals, or both, to the
serial configuration device. The configuration device provides data on its serial data
output (DATA) pin, which connects to the DATA0 input of the Arria II devices.
You can configure multiple Arria II devices using a single serial configuration device.
Cascade multiple Arria II devices using the chip-enable (nCE) and chip-enable-out
(nCEO) pins. The first device in the chain must have its nCE pin connected to GND. You
must connect its nCEO pin to the nCE pin of the next device in the chain. When the first
device captures all its configuration data from the bitstream, it drives the nCEO pin
low, enabling the next device in the chain. You must leave the nCEO pin of the last
device unconnected. The nCONFIG, nSTATUS, CONF_DONE, DCLK, and DATA0 pins of each
device in the chain are connected (refer to
The first Arria II device in the chain is the configuration master and controls
configuration of the entire chain. You must connect its MSEL pins to select the AS
configuration scheme. The remaining Arria II devices are configuration slaves. You
must connect their MSEL pins to select the PS configuration scheme. Any other Altera
device that supports PS configuration can also be part of the chain as a configuration
slave.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Figure
AS and Fast AS Configuration (Serial Configuration Devices)
9–7).
December 2010 Altera Corporation