EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 486

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–100
Table 1–32. ALTGX Megafunction 8B/10B Encoder Ports for Arria II Devices
Table 1–33. ALTGX Megafunction Transmitter PMA Ports for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
tx_
bitslipboundaryselect
tx_ctrlenable
tx_dispval
tx_forcedisp
tx_invpolarity
fixedclk
tx_dataout
Port Name
Port Name
Table 1–32
megafunction.
Table 1–33
megafunction.
Input/Output
Input/Output
Output
Input
Input
Input
Input
Input
Input
lists the 8B/10B encoder port names and descriptions for the ALTGX
lists the transmitter PMA port names and descriptions for the ALTGX
125-MHz clock for receiver detect and offset cancellation in PCIe mode.
Transmitter serial data output port.
Indicates the number of bits to slip at the transmitter for word alignment at the
receiver.
8B/10B encoder /Kx.y/ or /Dx.y/ control.
When asserted high, the 8B/10B encoder encodes the data on the tx_datain
port as a /Kx.y/ control code group. When de-asserted low, it encodes the data
on the tx_datain port as a /Dx.y/ data code group. The width of this signal
depends on the channel width shown below:
Channel Width
8B/10B encoder force disparity value. A high level on the tx_dispval signal
when the tx_forcedisp signal is asserted high forces the 8B/10B encoder to
encode the data on the tx_datain port with a negative starting running
disparity. A low level on the tx_dispval signal when the tx_forcedisp
signal is asserted high forces the 8B/10B encoder to encode the data on the
tx_datain port with a positive starting running disparity. The width of this
signal depends on the channel width shown below:
Channel Width
8B/10B encoder force disparity control. When asserted high, it forces the
8B/10B encoder to encode the data on the tx_datain port with a positive or
negative disparity, depending on the tx_dispval signal level. When
de-asserted low, the 8B/10B encoder encodes the data on the tx_datain port
according to the 8B/10B running disparity rules. The width of this signal
depends on the channel width shown below:
Channel Width
Asynchronous transmitter polarity inversion control. Useful feature for
correcting situations where the positive and negative signals of the differential
serial link are accidentally swapped during board layout. When asserted high
the polarity of every bit of the 8-bit or 10-bit input data to the serializer is
inverted.
16
16
8
8
16
8
tx_ctrlenable
tx_dispval
tx_forcedisp
1
2
1
2
1
2
Chapter 1: Transceiver Architecture in Arria II Devices
Description
Description
December 2010 Altera Corporation
Transceiver Port List