EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 336

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–56
Table 9–19. Remote System Upgrade Registers
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Shift
Control
Update
Status
Register
Remote System Upgrade Registers
This register is accessible by the logic array and allows the update, status, and control registers to be
written and sampled by user logic.
This register contains the current page address, user watchdog timer settings, and one bit specifying
whether the current configuration is a factory configuration or an application configuration. During a read
operation in an application configuration, this register is read into the shift register. When a
reconfiguration cycle is initiated, the contents of the update register are written into the control register.
This register contains data similar to that in the control register. However, it can only be updated by the
factory configuration by shifting data into the shift register and issuing an update operation. When a
reconfiguration cycle is triggered by the factory configuration, the control register is updated with the
contents of the update register. During a capture in a factory configuration, this register is read into the
shift register.
This register is written to by the remote system upgrade circuitry on every reconfiguration to record the
cause of the reconfiguration. This information is used by the factory configuration to determine the
appropriate action following a reconfiguration. During a capture cycle, this register is read into the shift
register.
The remote system upgrade block contains a series of registers that store the page
addresses, watchdog timer settings, and status information.
registers.
The remote system upgrade control and status registers are clocked by the 10-MHz
internal oscillator (the same oscillator that controls the user watchdog timer).
However, the remote system upgrade shift and update registers are clocked by the
user clock input (RU_CLK).
Remote System Upgrade Control Register
The remote system upgrade control register stores the application configuration page
address and user watchdog timer settings. The control register functionality depends
on the remote system upgrade mode selection. In remote update mode, the control
register page address bits are set to all zeros (24'b0 = 0×000000) at power up to load
the factory configuration. A factory configuration in remote update mode has write
access to this register.
The control register bit positions are shown in
the figure, the numbers show the bit position of a setting within a register. For
example, bit number 25 is the enable bit for the watchdog timer.
Figure 9–26. Remote System Upgrade Control Register
37 36 35 34 33 32 31 30 29 28 27 26
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Wd_timer[11..0]
Description
Wd_en
Figure 9–26
25
24 23 22 .. 3
Dedicated Remote System Upgrade Circuitry
PGM[23..0]
and listed in
December 2010 Altera Corporation
Table 9–19
2
1
lists these
Table
AnF
0
9–20. In